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LWR
31
26 25
LWR
1 0 0 1 1 0
6
Format:
LWR rt, offset (base)
Description:
This instruction can be used in combination with the LWL instruction to load a register with four consecutive bytes
from memory, when the bytes cross a word boundary. LWR loads the right portion of the register with the
appropriate part of the low-order word; LWL loads the left portion of the register with the appropriate part of the
high-order word.
The LWR instruction adds its sign-extended 16-bit offset to the contents of general register base to form a virtual
address that can specify an arbitrary byte. It reads bytes only from the word in memory that contains the specified
starting byte. From one to four bytes will be loaded, depending on the starting byte specified. In 64-bit mode, the
loaded word is sign-extended.
Conceptually, it starts at the specified byte in memory and loads that byte into the low-order (right-most) byte of the
register; then it loads bytes from memory into the register until it reaches the high-order byte of the word in
memory. The most significant (left-most) byte(s) of the register will not be changed.
7
address 4
3
address 0
518
APPENDIX A MIPS III INSTRUCTION SET DETAILS
Load Word Right (1/3)
21 20
base
rt
5
5
memory
6
5
4
2
1
0
LWR $24, 1 ($0)
Preliminary User's Manual S15543EJ1V0UM
16 15
before
A
after
A
LWR
offset
16
register
B
C
D
$24
$24
3
2
1
0
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