NEC uPD98433S9-K6 Manuals

Manuals and User Guides for NEC uPD98433S9-K6. We have 1 NEC uPD98433S9-K6 manual available for free PDF download: Preliminary User's Manual

NEC uPD98433S9-K6 Preliminary User's Manual

NEC uPD98433S9-K6 Preliminary User's Manual (142 pages)

10/100/1000 Mbps Ethernet Controller

Brand: NEC | Category: Controller | Size: 1 MB

Table of Contents

Table of Contents
7
Chapter 1 Overview

11
- Features
  
  11
- Ordering Information
  
  11
- Pin Configuration
  
  12
- Internal Block Diagram
  
  17
- Sample System Configuration
  
  17
Chapter 2 Pin Functions

18
Chapter 3 Function Description

28
- System Configuration
  
  28
- Function Blocks
  
  29
  - MAC Module
    29
  - PCS Module
    30
  - Station Address Logic (SAL) Module
    30
  - Statistics Counter (STAT) Module
    30
  - On-Chip FIFO
    30
  - FIFO Bus Module
    30
  - MII Management Module
    30
  - Register Bus Module
    31
  - Operation Clocks
    31
- Frame Formats
  
  32
- Transmit Operation
  
  33
- Receive Operations
  
  37
  - Preamble and SFD Detection
    37
  - Length Field Check
    37
  - CRC Check
    37
  - Packet Filtering
    37
  - Address Filtering
    38
  - Receive FIFO Overflow
    38
  - Clearing Receive FIFO
    39
  - Adding Status Information
    39
  - Receive Status Information
    40
- Full-Duplex Operation
  
  41
  - RBYT Field
    41
- System Bus Interface
  
  42
- Network Interface
  
  53
- Flow Control
  
  57
- Back Pressure
  
  61
- Operations on VLAN Frames
  
  61
  - VLAN Frame Detection
    61
  - VLAN Frame Reception
    61
  - VLAN Frame Transmission
    61
- Statistics Counters
  
  61
- Loopback
  
  62
- Low Power Mode
  
  62
- Software Reset
  
  63
- Turning Power on
  
  64
Chapter 4 Register Description

65
- Control Register Map
  
  65
- Port Configuration Registers
  
  67
- Global Registers
  
  99
- PCS Configuration Registers
  
  104
  - Pause Order of Precedence Resolution Table
    107
Chapter 5 Statistics Counters

114
Chapter 6 Jtag Boundary Scan

129
- Features
  
  129
- Internal Configuration of Boundary Scan Circuit
  
  130
  - Instruction Register
    130
  - TAP (Test Access Port) Controller
    130
  - Bypass Register
    130
  - Boundary Scan Register
    130
- Pin Function
  
  131
  - TCK (JTAG Test Clock) Pin
    131
  - TMS (JTAG Test Mode Select) Pin
    131
  - TDI (JTAG Test Data Input) Pin
    131
  - TDO (JTAG Test Data Output) Pin
    131
  - TRST# (JTAG Reset) Pin
    131
- Operation Description
  
  132
  - TAP Controller
    132
  - TAP Controller State
    132
- TAP Controller Operation
  
  137
  - Operation in each Controller State
    137
- Initializing TAP Controller
  
  140
- Instruction Register
  
  140
  - BYPASS Instruction
    141
  - EXTEST Instruction
    141
  - SAMPLE/PRELOAD Instruction
    141

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