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BGEZAL
Branch On Greater Than Or Equal To Zero And Link
31
26 25
REGIMM
0 0 0 0 0 1
6
Format:
BGEZAL rs, offset
Description:
A branch target address is computed from the sum of the address of the instruction in the delay slot and the 16-bit
offset, shifted left two bits and sign-extended. Unconditionally, the address of the instruction after the delay slot is
placed in the link register, r31 . If the contents of general register rs are zero or greater when compared to zero,
then the program branches to the target address, with a delay of one instruction.
General register rs may not be general register r31 , because such an instruction is not restartable. An attempt to
execute this instruction is not trapped, however.
Operation:
target ← (offset
32
T:
condition ← (GPR [rs]
GPR [31] ← PC + 8
T+1: if condition then
PC ← PC + target
endif
target ← (offset
64
T:
condition ← (GPR [rs]
GPR [31] ← PC + 8
T+1: if condition then
PC ← PC + target
endif
Exceptions:
None
APPENDIX A MIPS III INSTRUCTION SET DETAILS
21 20
16 15
BGEZAL
rs
1 0 0 0 1
5
5
14
2
)
|| offset || 0
15
= 0)
31
46
2
)
|| offset || 0
15
= 0)
63
Preliminary User's Manual S15543EJ1V0UM
BGEZAL
offset
16
0
451
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