NEC uPD98502 User Manual page 479

DMACC
Doubleword Multiply and Accumulate (3/3)
Operation:
64, sat=0, us=0 (DMACC instruction)
temp1 ← ((GPR[rs]
T:
temp2 ← temp1 + LO
LO ← temp2
GPR[rd] ← LO
64, sat=0, us=1 (DMACCU instruction)
temp1 ← (0
T:
temp2 ← temp1 + LO
LO ← temp2
GPR[rd] ← LO
64, sat=1, us=0 (DMACCS instruction)
temp1 ← ((GPR[rs]
T:
temp2 ← saturation(temp1 + LO)
LO ← temp2
GPR[rd] ← LO
64, sat=1, us=1 (DMACCUS instruction)
temp1 ← (0
T:
temp2 ← saturation(temp1 + LO)
LO ← temp2
GPR[rd] ← LO
Exceptions:
Reserved instruction exception (32-bit user mode/supervisor mode)
APPENDIX A MIPS III INSTRUCTION SET DETAILS
32
) || GPR [rs]) * ((GPR[rt]
31
32 32
|| GPR [rs]) * (0 || GPR [rt])
32
) || GPR [rs]) * ((GPR[rt]
31
32 32
|| GPR [rs]) * (0 || GPR [rt])
Preliminary User's Manual S15543EJ1V0UM
32
) || GPR [rt])
31
32
) || GPR [rt])
31
DMACC
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