P_Iimr (Internal Bus Interrupt Mask Register) - NEC uPD98502 User Manual

7.5.10 P_IIMR (Internal Bus Interrupt Mask Register)

IIMR register masks the interruption for each corresponding event. A mask bit, which locates in the same bit
position to a corresponding bit in IGSR, controls interruption triggered by the event. When a bit of this register is reset
to '0', the corresponding bit of the IGSR is masked. If it is set to '1', the corresponding bit is unmasked. When the
mask bit is reset and the bit in IGSR is set, the PCI Controller sets the interrupt signal to the V
Bits Field
31:16 PUINT
15:11 Reserved
10 IPREQ
9 SWRDN
8 DPERR
7 SSERR
6 RMABT
5 RTABT
4 STABT
3 PFDSC
2 RTYTE
1 PRBER
0 PWBER
396
CHAPTER 7 PCI CONTROLLER
R/W Default
Internal PCI
bus
R R/W 0000H
- - 0H
R R 0
R/W R 0
R R 0
R R 0
R R 0
R R 0
R R 0
R R 0
R R 0
R R 0
R R 0
Preliminary User's Manual S15543EJ1V0UM
Description
Interrupts which can be defined by the system the chip is used.
If '1' is written to this field from internal bus side, an interrupt to
PCI-Host is asserted.
Hardwired to '0H'
The transition of PPMI Power state issued.
'1' indicates that the V 4120A issues the transition of power state
R
of The PCI Controller.
Software Reset done.
'1' indicates that the software reset has been done.
Detected PCI Parity Error.
'1' indicates that the PCI Controller has detected a parity error on
PCI bus.
Signaled SERR#.
'1' indicates that the PCI Controller has asserted SERR_B.
Received Master Abort.
'1' indicates that the PCI Controller has received Master Abort as
master.
Received Target Abort.
'1' indicates that the PCI Controller has received Target Abort as
master.
Signaled Target Abort.
'1' indicates that the PCI Controller has executed Target Abort as
target.
PCI FIFO discarded.
'1' indicates that the PCI Controller has discarded the data for
read-delayed-transaction in FIFO, because the same issue has
15
not been repeated within 2 clock.
Retry Timer Expired.
'1' indicates that Retry Timer has expired and the PCI Controller
abandons the retry-access. See 7.2.3.1 (5).
Internal bus Error in read transaction
'1' indicates that the PCI Controller has received Bus Error on
internal bus during read transaction as master.
Internal bus Error in write transaction
'1' indicates that the PCI Controller has received Bus Error on
internal bus during write transaction as master.
4120A.
R