Table of Contents
Advertisement
LDR
Given a doubleword in a register and a doubleword in memory, the operation of LDR is as follows:
LDR
Register
Memory
Remark LEM
Little-endian memory (BigEndianMem = 0)
Type
AccessType (see Table 2-3. Byte Specification Related to Load and Store Instructions)
sent to memory
Offset
pAddr2..0 sent to memory
Exceptions:
TLB refill exception
TLB invalid exception
Bus error exception
Address error exception
Reserved instruction exception (32-bit user mode/supervisor mode)
510
APPENDIX A MIPS III INSTRUCTION SET DETAILS
Load Doubleword Right (3/3)
A
B
C
I
J
K
vAddr2..0
Destination
0
I J K L MN O P
1
A I J K L M N O
2
A B I J K L M N
3
A B C I J K L M
4
A B C D I J K L
5
A B C D E I J K
6
A B C D E F I J
7
A B C D E F G I
Preliminary User's Manual S15543EJ1V0UM
D
E
F
G
L
M
N
O
Type
Offset
(LEM)
7
0
6
1
5
2
4
3
3
4
2
5
1
6
0
7
LDR
H
P
Advertisement
Table of Contents
