Table of Contents
Advertisement
ADD
31
26 25
SPECIAL
0 0 0 0 0 0
6
Format:
ADD rd, rs, rt
Description:
The contents of general register rs and the contents of general register rt are added to form the result. The result
is placed into general register rd . In 64-bit mode, the operands must be valid sign-extended, 32-bit values.
An overflow exception occurs if the carries out of bits 30 and 31 differ (2's complement overflow). The destination
register rd is not modified when an integer overflow exception occurs.
Operation:
GPR [rd] ← GPR [ rs] + GPR [ rt]
32
T:
temp ← GPR [ rs] + GPR [ rt]
64
T:
GPR [rd] ← (temp
Exceptions:
Integer overflow exception
436
APPENDIX A MIPS III INSTRUCTION SET DETAILS
Add
21 20
16 15
rs
rt
5
5
32
)
|| temp
31
31...0
Preliminary User's Manual S15543EJ1V0UM
11 10
6 5
0
rd
0 0 0 0 0
5
5
ADD
0
ADD
1 0 0 0 0 0
6
Advertisement
Table of Contents
