NEC uPD98502 User Manual page 153

2.5.4.10 System call exception
(1) Cause
A System Call exception occurs during an attempt to execute the SYSCALL instruction. This exception is not
maskable.
(2) Processing
The common exception vector is used for this exception, and the Sys code in the ExcCode field of the Cause
register is set.
The EPC register contains the address of the SYSCALL instruction unless it is in a branch delay slot, in which
case the EPC register contains the address of the preceding branch instruction.
If the SYSCALL instruction is in a branch delay slot, the BD bit of the Status register is set to 1; otherwise this bit is
cleared.
(3) Servicing
When this exception occurs, control is transferred to the applicable system routine.
To resume execution, the EPC register must be altered so that the SYSCALL instruction does not re-execute; this
is accomplished by adding a value of 4 to the EPC register before returning.
If a SYSCALL instruction is in a branch delay slot, interpretation (decoding) of the branch instruction is required to
resume execution.
2.5.4.11 Breakpoint exception
(1) Cause
A Breakpoint exception occurs when an attempt is made to execute the BREAK instruction. This exception is not
maskable.
(2) Processing
The common exception vector is used for this exception, and the Bp code in the ExcCode field of the Cause
register is set.
The EPC register contains the address of the instruction that caused the exception. However, if this instruction is
in a branch delay slot, the EPC register contains the address of the preceding jump or branch instruction, and the
BD bit of the Cause register is set to 1.
(3) Servicing
When the Breakpoint exception occurs, control is transferred to the applicable system routine. Additional
distinctions can be made by analyzing the unused bits of the BREAK instruction (bits 25 to 6), and loading the
contents of the instruction whose address the EPC register contains.
To resume execution, the EPC register must be altered so that the BREAK instruction does not re-execute; this is
accomplished by adding a value of 4 to the EPC register before returning.
If a BREAK instruction is in a branch delay slot, interpretation (decoding) of the branch instruction is required to
resume execution.
CHAPTER 2 V 4120A
R
Preliminary User's Manual S15543EJ1V0UM
153