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DADD
31
26 25
SPECIAL
0 0 0 0 0 0
6
Format:
DADD rd, rs, rt
Description:
The contents of general register rs and the contents of general register rt are added to form the result. The result
is placed into general register rd .
An overflow exception occurs if the carries out of bits 62 and 63 differ (2's complement overflow). The destination
register rd is not modified when an integer overflow exception occurs.
This operation is defined in 64-bit mode or in 32-bit kernel mode. Execution of this instruction in 32-bit user or
supervisor mode causes a reserved instruction exception.
Operation:
GPR [rd] ← GPR [rs] + GPR [rt]
64
T:
Exceptions:
Integer overflow exception
Reserved instruction exception (32-bit user mode/supervisor mode)
APPENDIX A MIPS III INSTRUCTION SET DETAILS
Doubleword Add
21 20
16 15
rs
rt
5
5
Preliminary User's Manual S15543EJ1V0UM
11 10
6 5
0
rd
0 0 0 0 0
5
5
DADD
0
DADD
1 0 1 1 0 0
6
469
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