Branch Instructions - NEC uPD98502 User Manual

There are special symbols used in the instruction formats of Tables 2-17 through 2-21.
REGIMM
Sub
CO
BC
br
op
Instruction
Branch On Equal BEQ rs, rt, offset
If the contents of register rs are equal to that of register rt, the program branches to the target address.
Branch On Not Equal BNE rs, rt, offset
If the contents of register rs are not equal to that of register rt, the program branches to the target
address.
Branch On Less Than BLEZ rs, offset
Or Equal To Zero If the contents of register rs are less than or equal to zero, the program branches to the target address.
Branch On Greater BGTZ rs, offset
Than Zero If the contents of register rs are greater than zero, the program branches to the target address.
Instruction
Branch On Less Than BLTZ rs, offset
Zero If the contents of register rs are less than zero, the program branches to the target address.
Branch On Greater BGEZ rs, offset
Than Or Equal To Zero If the contents of register rs are greater than or equal to zero, the program branches to the target
address.
Branch On Less Than BLTZAL rs, offset
Zero And Link The address of the instruction that follows delay slot is stored to register r31 (link register). If the
contents of register rs are less than zero, the program branches to the target address.
Branch On Greater BGEZAL rs, offset
Than Or Equal To Zero The address of the instruction that follows delay slot is stored to register r31 (link register). If the
And Link contents of register rs are greater than or equal to zero, the program branches to the target address.
Instruction
Branch On BC0T offset
Coprocessor 0 True Adds the 16-bit offset (shifted left by two bits and sign extended to 32 bits) to the address of the
instruction in the delay slot to calculate the branch target address.
If the conditional signal of the coprocessor 0 is true, the program branches to the target address with
one-instruction delay.
Branch On BC0F offset
Coprocessor 0 False Adds the 16-bit offset (shifted left by two bits and sign extended to 32 bits) to the address of the
instruction in the delay slot to calculate the branch target address.
If the conditional signal of the coprocessor 0 is false, the program branches to the target address with
one-instruction delay.
CHAPTER 2 V
: Opcode
: Sub-operation code
: Sub-operation identifier
: BC sub-operation code
: Branch condition identifier
: Operation code
Table 2-17. Branch Instructions
Format and Description
Format and Description
Format and Description
Preliminary User's Manual S15543EJ1V0UM
4120A
R
rs
op
rs sub
REGIMM
COP0 BC
rt offset
offset
offset
br
79