Registers; Register Map - NEC uPD98502 User Manual

3.2 Registers

3.2.1 Register map

Following Table summarizes the controller's register set. The base address for the set is 1000_0000H in the
physical address space.
Offset Address Register Name
1000_0000H S_GMR
1000_0004H S_GSR
1000_0008H S_ISR
1000_000CH S_IMR
1000_0010H S_NSR
1000_0014H S_NER
1000_0018H S_VER
1000_001CH S_IOR
1000_0020H: N/A
1000_002CH
1000_0030H S_WRCR
1000_0034H S_WRSR
1000_0038H S_PWCR
1000_003CH S_PWSR
1000_0040H: N/A
1000_0048H
1000_004CH ITCNTR
1000_0050H ITSETR
1000_0054H: N/A
1000_007CH
1000_0080H UARTRBR
1000_0080H UARTTHR
1000_0080H UARTDLL
1000_0084H UARTIER
1000_0084H UARTDLM
1000_0088H UARTIIR
1000_0088H UARTFCR
1000_008CH UARTLCR
1000_0090H UARTMCR
1000_0094H UARTLSR
1000_0098H UARTMSR
1000_009CH UARTSCR
1000_00A0H DSUCNTR
1000_00A4H DSUSETR
1000_00A8H DSUCLRR
1000_00ACH DSUTIMR
1000_00B0H TMMR
1000_00B4H TM0CSR
1000_00B8H TM1CSR
1000_00BCH TM0CCR
1000_00C0H TM1CCR
1000_00C4H: N/A
1000_00CCH
1000_00D0H ECCR
1000_00D4H ERDR
CHAPTER 3 SYSTEM CONTROLLER
R/W Access
R/W W/H/B General Mode Register
R W/H/B General Status Register
RC W/H/B Interrupt Status Register
R/W W/H/B Interrupt Mask Register
RC W/H/B NMI Status Register
R/W W/H/B NMI Enable Register
R W/H/B Version Register
R/W W/H/B IO Port Register
- - Reserved for future use
W W/H/B Warm Reset Control Register
R W/H/B Warm Reset Status Register
R/W W/H/B Power Control Register
R W/H/B Power Control Status Register
- - Reserved for future use
R/W W/H/B IBUS Timeout Timer Control Register
R/W W/H/B IBUS Timeout Timer Set Register
- - Reserved for future use
R W/H/B UART, Receiver Buffer Register [DLAB=0,READ]
W W/H/B UART, Transmitter Holding Register [DLAB=0,WRITE]
R/W W/H/B UART, Divisor Latch LSB Register [DLAB=1]
R/W W/H/B UART, Interrupt Enable Register [DLAB=0]
R/W W/H/B UART, Divisor Latch MSB Register [DLAB=1]
R W/H/B UART, Interrupt ID Register [READ]
W W/H/B UART, FIFO control Register [WRITE]
R/W W/H/B UART, Line control Register
R/W W/H/B UART, Modem Control Register
R/W W/H/B UART, Line status Register
R/W W/H/B UART, Modem Status Register
R/W W/H/B UART, Scratch Register
R/W W/H/B DSU Control Register
R/W W/H/B DSU Dead Time Set Register
W W/H/B DSU Clear Register
R W/H/B DSU Elapsed Time Register
R/W W/H/B Timer Mode Register
R/W W/H/B Timer CH0 Count Set Register
R/W W/H/B Timer CH1 Count Set Register
R W/H/B Timer CH0 Current Count Register
R W/H/B Timer CH1 Current Count Register
- - Reserved for future use
W W/H/B EEPROM Command Control Register
R W/H/B EEPROM Read Data Register
Preliminary User's Manual S15543EJ1V0UM
Description
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