Floating-Point Unit (Fpu); System Control Coprocessor (Cp0) Register Definitions - NEC uPD98502 User Manual

Table 2-1. System Control Coprocessor (CP0) Register Definitions
Register
Number
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21 to 25
26
27
28
29
30
31
Note This register is defined to maintain compatibility with the V
the µ PD98502 hardware.

2.1.6 Floating-point unit (FPU)

The V 4120A does not support the floating-point unit (FPU). Coprocessor Unusable exception will occur if any
R
FPU instructions are executed. If necessary, FPU instructions should be emulated by software in an exception
handler.
64
CHAPTER 2 V
Register Name
Index Programmable pointer to TLB array
Random Pseudo-random pointer to TLB array (read only)
EntryLo0 Low half of TLB entry for even VPN
EntryLo1 Low half of TLB entry for odd VPN
Context Pointer to kernel virtual PTE in 32-bit mode
PageMask TLB page mask
Wired Number of wired TLB entries

Reserved for future use
BadVAddr Virtual address where the most recent error occurred
Count Timer count
EntryHi High half of TLB entry (including ASID)
Compare Timer compare
Status Status register
Cause Cause of last exception
EPC Exception Program Counter
PRId Processor revision identifier
Config Configuration register (specifying memory mode system)
LLAddr Reserved for future use
WatchLo Memory reference trap address low bits
WatchHi Memory reference trap address high bits
XContext Pointer to kernel virtual PTE in 64-bit mode

Reserved for future use
Note
Cache parity bits
PErr
Note
Index and status of cache error
CacheErr
TagLo Cache Tag register (low)
TagHi Cache Tag register (high)
ErrorEPC Error Exception Program Counter

Reserved for future use
Preliminary User's Manual S15543EJ1V0UM
4120A
R
Description
4100™. This register is not used in
R