En_Txfcr (Transmit Fifo Control Register); Tx Fifo Control Mechanism - NEC uPD98502 User Manual

5.2.27 En_TXFCR (Transmit FIFO Control Register)

Bits Field
31:16 TPTV
15:10 TX_DRTH
9:8 Reserved
7:2 TX_FRTH
1:0 Reserved
From internal bus
Request
New data
Request
New data
Request
New data
CHAPTER 5 ETHERNET CONTROLLER
R/W Default
R/W FFFFH Transmit Pause Timer Value:
R/W 10H Transmit Drain Threshold Level:
This threshold is enable to the transmit data to the MAC Control Block form
the Tx-FIFO. If the transfer data is not completed by DMAC and the buffer
empty pointer exceed this pointer, this MAC Control Block sends an Abort
Packet. Please see the Figure 5-2. This is a word pointer.
R/W 0 Reserved for future use. Write 0s.
R/W 30H Transmit Fill Threshold Level:
This threshold is enable to transmit data to the FIFO from the internal bus
through the DMAC of this block. Please see the Figure 5-2. This is a word
pointer.
R/W 0 Reserved for future use. Write 0s.
Figure 5-2. Tx FIFO Control Mechanism
Tx_FIFO (256 Bytes)
FLTH
FLTH
FLTH
FLTH
Preliminary User's Manual S15543EJ1V0UM
Description
To MAC Control Block
Sending
Abort
DRTH
DRTH
DRTH
Finish
Packet
EOF
Transmit
DRTH
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