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SDR
Given a doubleword in a register and a doubleword in memory, the operation of SDR instruction is as follows:
SDR
Register
Memory
Remark LEM
Little-endian memory (BigEndianMem = 0)
Type
AccessType (see Table 2-3. Byte Specification Related to Load and Store Instructions)
sent to memory
Offset
pAddr2..0 sent to memory
Exceptions:
TLB refill exception
TLB invalid exception
TLB modification exception
Bus error exception
Address error exception
Reserved instruction exception (32-bit user mode/supervisor mode)
APPENDIX A MIPS III INSTRUCTION SET DETAILS
Store Doubleword Right (3/3)
A
B
C
I
J
K
vAddr2..0
Destination
0
A B C D E F G H
1
B C D E F G H P
2
C D E F G H O P
3
D E F G H N O P
4
E F G HMN O P
5
F G H L MN O P
6
G H K L MN O P
7
H J K L MN O P
Preliminary User's Manual S15543EJ1V0UM
D
E
F
G
L
M
N
O
Type
Offset
(LEM)
7
0
6
1
5
2
4
3
3
4
2
5
1
6
0
7
SDR
H
P
545
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