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A.4 System Control Coprocessor (CP0) Instructions
There are some special limitations imposed on operations involving CP0 that is incorporated within the CPU.
Although load and store instructions to transfer data to/from coprocessors and to move control to/from coprocessor
instructions are generally permitted by the MIPS architecture, CP0 is given a somewhat protected status since it has
responsibility for exception handling and memory management. Therefore, the move to/from coprocessor instructions
are the only valid mechanism for writing to and reading from the CP0 registers.
Several CP0 instructions are defined to directly read, write, and probe TLB entries and to modify the operating
modes in preparation for returning to User mode or interrupt-enabled states.
A.5 CPU Instruction
This section describes the functions of CPU instructions in detail for both 32-bit address mode and 64-bit address
mode.
The exception that may occur by executing each instruction is shown in the last of each instruction's description.
For details of exceptions and their processes, see Section 2.5 Exception Processing.
APPENDIX A MIPS III INSTRUCTION SET DETAILS
Preliminary User's Manual S15543EJ1V0UM
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