Reset Configuration - NEC uPD98502 User Manual

1.10 Reset Configuration

The falling edge of Clock Control Unit (CCU)'s reset line (RST_B) serves as the µ PD98502's internal reset. The
System Controller generates the IBUS reset signal using RST_B for the global reset of the µ PD98502. After 4 IBUS
clock (SDCLK), the System Controller deasserts the IBUS reset signal synchronously with IBUS clock (66 MHz). And
also the System Controller generates the internal Cold Reset signal and Hot Reset signal for performing the cold reset
4120A. Once power to the µ PD98502 is established, the System Controller asserts internal CLKSET signal,
of V
R
internal Cold Reset (COLDRST#) signal and internal Hot Reset (HOTRST#) signal at the falling edge of RST_B
signal. After 2 V 4120A clock (internal VCLOCK) cycles at rising edge of the RST_B, the System Controller deasserts
R
the CLKSET signal synchronously with "clkm". Then 16 "clkm" cycles (see section 1.12) at the rising edge of the
RST_B signal, the System Controller deasserts the COLDRST# synchronously with "clkm". And also the System
Controller deasserts the HOTRST# synchronously with "clkm" after 16 "clkm" clock cycles at deassertion of the
COLDRST#.
USB
MII
MII
PCI
54
CHAPTER 1 INTRODUCTION
Figure 1-11. Reset Configuration
µ µ µ µ PD98502
ibrset
USB Controller
usbwrst
usbrdy
ibrset
Ethernet
Controller
#1
macwrst
macrdy
ibrset
Ethernet
Controller
#2
mac2wrst
mac2rdy
ibrset
PCI
Controller
pciwrst
pcirdy
Preliminary User's Manual S15543EJ1V0UM
ibrset
ATM Cell Processor
PHY-MGR
atmwrst atmrdy
atmwrst atmrdy
usbwrst Boot ROM
usbrdy
ibrset
macwrst
macrdy
reset
mac2wrst
mac2rdy
System Controller
CLKSET
pciwrst
COLDRST#
pcirdy HOTRST#
cresetb
V 4120A RISC
R
Processor Core
UTOPIA2
SDRAM
UART
RESET