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LDL
The contents of general register rt are internally bypassed within the processor so that no NOP is needed between
an immediately preceding load instruction which specifies register rt and a following LDL (or LDR) instruction which
also specifies register rt .
No address error exceptions due to alignment are possible.
This operation is defined in 64-bit mode or in 32-bit kernel mode. Execution of this instruction in 32-bit user or
supervisor mode causes a reserved instruction exception.
Operation:
vAddr ← ((offset
64
T:
(pAddr, uncached) ← AddressTranslation (vAddr, DATA)
pAddr ← p Addr
if BigEndianMem = 0 then
pAddr ← pAddr
endif
byte ← vAddr
mem ← LoadMemory (uncached, byte, pAddr, vAddr, DATA)
GPR [rt] ← mem
506
APPENDIX A MIPS III INSTRUCTION SET DETAILS
Load Doubleword Left (2/3)
48
)
|| offset
) + GPR [base]
15
15..0
|| (pAddr
xor ReverseEndian
PSIZE - 1..3
2..0
3
|| 0
PSIZE - 1..3
3
xor BigEndianCPU
2..0
|| GPR [rt]
7 + 8 * byte..0
55 – 8 * byte..0
Preliminary User's Manual S15543EJ1V0UM
3
)
LDL
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