P_Pgsr (Pci-Side General Status Register) - NEC uPD98502 User Manual

7.5.9 P_PGSR (PCI-side General Status Register)

PGSR register shows the interrupt status of the PCI Controller to PCI-side (which means PCI-Host). When an
event that triggers interruption occurs, the PCI Controller sets a bit in PGSR corresponds to the type of incident. If the
interruption is not masked, the PCI Controller interrupts to PCI-Host using the interrupt signal.
Reading this register from PCI-side clears all of bits in the register.
Bits Field
31:16 IUINT
15:12 Reserved
11 PINTR
10 PSERI
9 PPERR
8 PPREQ
7 SRREQ
6 IRBER
5 IWBER
4 IFDSC
3 RDTAT
2 WRTAT
1 RDMAT
0 WRMAT
CHAPTER 7 PCI CONTROLLER
R/W Default
Internal PCI
bus
R R/W 0
- - 0
R R 0
R R 0
R R 0
R R 0
R R 0
R R 0
R R 0
R R 0
R R 0
R R 0
R R 0
R R 0
Preliminary User's Manual S15543EJ1V0UM
Description
Interrupts that can be defined by the system the chip is used.
When '1' is written to a bit in this field from PCI bus side, interrupt
to the V 4120A is asserted.
R
Hardwired to '0's.
Used only in Host-mode.
Interrupts from PCI-device occurred.
'1' indicates that a PCI-interruption occur.
Used only in Host-mode.
SERR_B from external PCI-devices is asserted.
'1' indicates that SERR_B is asserted.
PCI Parity Error.
'1' indicates that the PCI Controller has detected a parity error on
PCI bus.
The transition of PPMI Power state issued.
'1' indicates that PCI-Host issues the transition of power state of
The PCI Controller.
When this bit is set, the V 4120A should check PPCR register to
R
know which state the PCI Controller moves to.
Software Reset is issued.
'1' indicates that PCI-Host issues Software Reset, when PCI-Host
writes to SWRS register. the V
in PGSR register to a '1' after the completion of software reset.
Internal bus Error in read transaction.
'1' indicates that the PCI Controller has received Bus Error on
internal bus during read transaction as master.
Internal bus Error in write transaction.
'1' indicates that the PCI Controller has received Bus Error on
internal bus during write transaction as master.
Internal bus FIFO data discarded.
'1' indicates that the PCI Controller has discarded the data for
read-delayed-transaction in FIFO, because the same issue has
15
not been repeated within 2 clock.
PCI Target Abort in read transaction.
'1' indicates that the PCI Controller has received Target Abort on
PCI bus during read transaction as master.
PCI Target Abort in write transaction.
'1' indicates that the PCI Controller has received Target Abort on
PCI bus during write transaction as master.
PCI Master Abort in read transaction.
'1' indicates that the PCI Controller has received Master Abort on
PCI bus during read transaction as master.
PCI Master Abort in write transaction.
'1' indicates that the PCI Controller has received Master Abort on
PCI bus during write transaction as master.
4120A should be set SWRDN bit
R
395