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Figure 2-63. Cold Reset Exception Handling
(Hardware)
BD bit ← 1
ErrorEPC ← PC − 4
Update Config register bit
31:28||Undef(27:23)||22:6||Undef(5:0)
PC ← FFFF FFFF BFC0 0000H
(Software)
Servicing by NMI
exception routine
ERET
CHAPTER 2 V
4120A
R
Cold Reset
Exception
Yes
ERL=1?
No
Yes
M16=1?
(config20)
No
BD bit←1
Yes
No
Instruction
ErrorEPC←PC−4
in branch delay
ErrorEPC←EIM
slot?
BD bit ← 0
ErrorEPC ← PC
Random register ← 31
Wired register ← 0
Set Status register
BEV bit ← 1
TS bit ← 0
SR bit ← 0
ERL bit ← 1
• The processor provides no means
of distinguishing between an NMI
Yes
NMI?
exception and Soft Reset exception,
so that this must be determined at
the system level.
No
= 0
SR bit
= 1
Servicing by
Soft Reset
exception routine
Preliminary User's Manual S15543EJ1V0UM
Yes
No
Instruction
in delay slot?
BD bit←0
ErrorEPC← PC
ErrorEPC←EIM
Servicing by
Cold Reset
exception routine
163
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