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ADDU
31
26 25
SPECIAL
0 0 0 0 0 0
6
Format:
ADDU rd, rs, rt
Description:
The contents of general register rs and the contents of general register rt are added to form the result. The result
is placed into general register rd . No integer overflow exception occurs under any circumstances. In 64-bit mode,
the operands must be valid sign-extended, 32-bit values.
The only difference between this instruction and the ADD instruction is that ADDU never causes an integer
overflow exception.
Operation:
GPR [rd] ← GPR [ rs] + GPR [rt]
32
T:
temp ← GPR [ rs] + GPR [rt]
64
T:
GPR [rd] ← (temp
Exceptions:
None
APPENDIX A MIPS III INSTRUCTION SET DETAILS
Add Unsigned
21 20
16 15
rs
rt
5
5
32
)
|| temp
31
31...0
Preliminary User's Manual S15543EJ1V0UM
11 10
6 5
0
rd
0 0 0 0 0
5
5
ADDU
0
ADDU
1 0 0 0 0 1
6
439
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