NEC uPD98502 Manuals

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NEC uPD98502 User Manual

NEC uPD98502 User Manual (595 pages)

Brand: NEC | Category: Network Cable | Size: 3.1 MB
Table of contents
Table Of Contents3................................................................................................................................................................
Chapter 1 Introduction23................................................................................................................................................................
Features23................................................................................................................................................................
Ordering Information23................................................................................................................................................................
System Configuration24................................................................................................................................................................
Block Diagram (summary)25................................................................................................................................................................
Block Diagram (detail)26................................................................................................................................................................
Ibus27................................................................................................................................................................
Block Diagram Of Ibus27................................................................................................................................................................
System Controller28................................................................................................................................................................
Block Diagram Of System Controller28................................................................................................................................................................
Atm Cell Processor29................................................................................................................................................................
Block Diagram Of Atm Cell Processor29................................................................................................................................................................
Ethernet Controller30................................................................................................................................................................
Block Diagram Of Ethernet Controller30................................................................................................................................................................
Usb Controller31................................................................................................................................................................
Block Diagram Of Usb Controller31................................................................................................................................................................
Pci Controller32................................................................................................................................................................
Block Diagram Of Pci Bus Controller32................................................................................................................................................................
Pin Configuration (bottom View)33................................................................................................................................................................
Pin Function37................................................................................................................................................................
Power Supply37................................................................................................................................................................
System Pll Power Supply37................................................................................................................................................................
Usb Pll Power Supply37................................................................................................................................................................
System Control Interface38................................................................................................................................................................
Memory Interface39................................................................................................................................................................
Pci Interface41................................................................................................................................................................
Atm Interface43................................................................................................................................................................
Ethernet Interface45................................................................................................................................................................
Usb Interface46................................................................................................................................................................
Uart Interface47................................................................................................................................................................
Micro Wire Interface47................................................................................................................................................................
Parallel Port Interface47................................................................................................................................................................
Boundary Scan Interface47................................................................................................................................................................
I.c. – Open48................................................................................................................................................................
I.c.– Pull Down48................................................................................................................................................................
I.c. – Pull Down With Resistor48................................................................................................................................................................
I.c. – Pull Up48................................................................................................................................................................
I/o Register Map49................................................................................................................................................................
Memory Map53................................................................................................................................................................
Reset Configuration54................................................................................................................................................................
Interrupts55................................................................................................................................................................
Interrupt Signal Connection55................................................................................................................................................................
Clock Control Unit56................................................................................................................................................................
Block Diagram Of Clock Control Unit56................................................................................................................................................................
Internal Block Configuration58................................................................................................................................................................
Cpu Instruction Formats (32-bit Length Instruction)60................................................................................................................................................................
Data Formats And Addressing61................................................................................................................................................................
Little-endian Byte Ordering In Word Data61................................................................................................................................................................
Little-endian Byte Ordering In Double Word Data61................................................................................................................................................................
Misaligned Word Accessing (little-endian)62................................................................................................................................................................
Coprocessors (cp0)63................................................................................................................................................................
Cp0 Registers63................................................................................................................................................................
Floating-point Unit (fpu)64................................................................................................................................................................
System Control Coprocessor (cp0) Register Definitions64................................................................................................................................................................
Cpu Core Memory Management System (mmu)65................................................................................................................................................................
Translation Lookaside Buffer (tlb)65................................................................................................................................................................
Operating Modes65................................................................................................................................................................
Cache65................................................................................................................................................................
Instruction Pipeline66................................................................................................................................................................
Mips Iii Instruction Set Summary66................................................................................................................................................................
Mips Iii Isa Instruction Formats66................................................................................................................................................................
Mips Iii Isa Cpu Instruction Formats66................................................................................................................................................................
Instruction Classes67................................................................................................................................................................
Number Of Delay Slot Cycles Necessary For Load And Store Instructions67................................................................................................................................................................
Byte Specification Related To Load And Store Instructions68................................................................................................................................................................
Load/store Instruction69................................................................................................................................................................
Load/store Instruction (extended Isa)70................................................................................................................................................................
Alu Immediate Instruction71................................................................................................................................................................
Alu Immediate Instruction (extended Isa)72................................................................................................................................................................
Three-operand Type Instruction72................................................................................................................................................................
Three-operand Type Instruction (extended Isa)73................................................................................................................................................................
Shift Instruction73................................................................................................................................................................
Shift Instruction (extended Isa)74................................................................................................................................................................
Multiply/divide Instructions75................................................................................................................................................................
Multiply/divide Instructions (extended Isa)76................................................................................................................................................................
Number Of Stall Cycles In Multiply And Divide Instructions77................................................................................................................................................................
Number Of Delay Slot Cycles In Jump And Branch Instructions77................................................................................................................................................................
Jump Instruction78................................................................................................................................................................
Branch Instructions79................................................................................................................................................................
Branch Instructions (extended Isa)80................................................................................................................................................................
Special Instructions81................................................................................................................................................................
Special Instructions (extended Isa) (1/2)81................................................................................................................................................................
Special Instructions (extended Isa) (2/2)82................................................................................................................................................................
System Control Coprocessor (cp0) Instructions (1/2)82................................................................................................................................................................
System Control Coprocessor (cp0) Instructions (2/2)83................................................................................................................................................................
Pipeline84................................................................................................................................................................
Pipeline Stages84................................................................................................................................................................
Pipeline Stages (mips Iii Instruction Mode)84................................................................................................................................................................
Instruction Execution In The Pipeline85................................................................................................................................................................
Pipeline Activities (mips Iii)85................................................................................................................................................................
Operation In Each Stage Of Pipeline (mips Iii)86................................................................................................................................................................
Branch Delay87................................................................................................................................................................
Load Delay87................................................................................................................................................................
Branch Delay (in Mips Iii Instruction Mode)87................................................................................................................................................................
Pipeline Operation88................................................................................................................................................................
Add Instruction Pipeline Activities (in Mips Iii Instruction Mode)88................................................................................................................................................................
Jalr Instruction Pipeline Activities (in Mips Iii Instruction Mode)89................................................................................................................................................................
Beq Instruction Pipeline Activities (in Mips Iii Instruction Mode)90................................................................................................................................................................
Tlt Instruction Pipeline Activities91................................................................................................................................................................
Lw Instruction Pipeline Activities (in Mips Iii Instruction Mode)92................................................................................................................................................................
Sw Instruction Pipeline Activities (in Mips Iii Instruction Mode)93................................................................................................................................................................
Interlock And Exception Handling94................................................................................................................................................................
Relationship Among Interlocks, Exceptions, And Faults94................................................................................................................................................................
Correspondence Of Pipeline Stage To Interlock And Exception Conditions94................................................................................................................................................................
Pipeline Interlock95................................................................................................................................................................
Description Of Pipeline Exception95................................................................................................................................................................
Exception Detection96................................................................................................................................................................
Data Cache Miss Stall97................................................................................................................................................................
Cache Instruction Stall97................................................................................................................................................................
Load Data Interlock98................................................................................................................................................................
Md Busy Interlock99................................................................................................................................................................
Program Compatibility100................................................................................................................................................................
Memory Management System101................................................................................................................................................................
Virtual Address Space102................................................................................................................................................................
Virtual-to-physical Address Translation102................................................................................................................................................................
Bit Mode Virtual Address Translation104................................................................................................................................................................
User Mode Address Space106................................................................................................................................................................
Comparison Of Useg And Xuseg107................................................................................................................................................................
Supervisor Mode Address Space108................................................................................................................................................................
Bit And 64-bit Supervisor Mode Segments109................................................................................................................................................................
Kernel Mode Address Space111................................................................................................................................................................
Bit Kernel Mode Segments112................................................................................................................................................................
Cacheability And Xkphys Address Space114................................................................................................................................................................
Physical Address Space116................................................................................................................................................................
µ Pd98502 Physical Address Space116................................................................................................................................................................
System Control Coprocessor117................................................................................................................................................................
Cp0 Registers And Tlb117................................................................................................................................................................
Format Of A Tlb Entry118................................................................................................................................................................
Index Register119................................................................................................................................................................
Random Register119................................................................................................................................................................
Entrylo0 And Entrylo1 Registers120................................................................................................................................................................
Page Mask Register121................................................................................................................................................................
Cache Algorithm121................................................................................................................................................................
Mask Values And Page Sizes121................................................................................................................................................................
Positions Indicated By Wired Register122................................................................................................................................................................
Wired Register122................................................................................................................................................................
Entryhi Register123................................................................................................................................................................
Prid Register123................................................................................................................................................................
Config Register Format124................................................................................................................................................................
Lladdr Register125................................................................................................................................................................
Taglo Register125................................................................................................................................................................
Taghi Register125................................................................................................................................................................
Tlb Address Translation127................................................................................................................................................................
Exception Processing129................................................................................................................................................................
Exception Processing Operation129................................................................................................................................................................
Precision Of Exceptions130................................................................................................................................................................
Exception Processing Registers130................................................................................................................................................................
Cp0 Exception Processing Registers130................................................................................................................................................................
Context Register Format131................................................................................................................................................................
Badvaddr Register Format132................................................................................................................................................................
Count Register Format132................................................................................................................................................................
Compare Register Format133................................................................................................................................................................
Status Register Format134................................................................................................................................................................
Status Register Diagnostic Status Field135................................................................................................................................................................
Cause Register Format136................................................................................................................................................................
Cause Register Exception Code Field137................................................................................................................................................................
Epc Register Format138................................................................................................................................................................
Watchlo Register Format139................................................................................................................................................................
Watchhi Register Format139................................................................................................................................................................
Xcontext Register Format140................................................................................................................................................................
Parity Error Register Format140................................................................................................................................................................
Cache Error Register Format141................................................................................................................................................................
Errorepc Register Format141................................................................................................................................................................
Details Of Exceptions142................................................................................................................................................................
Bit Mode Exception Vector Base Addresses142................................................................................................................................................................
Exception Priority Order144................................................................................................................................................................
Exception Processing And Servicing Flowcharts158................................................................................................................................................................
Common Exception Handling159................................................................................................................................................................
Tlb/xtlb Refill Exception Handling161................................................................................................................................................................
Cold Reset Exception Handling163................................................................................................................................................................
Soft Reset And Nmi Exception Handling164................................................................................................................................................................
Initialization Interface165................................................................................................................................................................
Cold Reset165................................................................................................................................................................
Soft Reset165................................................................................................................................................................
Cache Memory168................................................................................................................................................................
Memory Organization168................................................................................................................................................................
Logical Hierarchy Of Memory168................................................................................................................................................................
Cache Organization169................................................................................................................................................................
Cache Support169................................................................................................................................................................
Instruction Cache Line Format170................................................................................................................................................................
Data Cache Line Format170................................................................................................................................................................
Cache Operations171................................................................................................................................................................
Cache Data And Tag Organization171................................................................................................................................................................
Cache States172................................................................................................................................................................
Cache State Transition Diagrams173................................................................................................................................................................
Data Cache State Diagram173................................................................................................................................................................
Instruction Cache State Diagram173................................................................................................................................................................
Cache Data Integrity174................................................................................................................................................................
Data Check Flow On Instruction Fetch174................................................................................................................................................................
Data Check Flow On Load Operations174................................................................................................................................................................
Data Check Flow On Store Operations175................................................................................................................................................................
Data Check Flow On Index_invalidate Operations175................................................................................................................................................................
Data Check Flow On Index_writeback_invalidate Operations176................................................................................................................................................................
Data Check Flow On Index_load_tag Operations176................................................................................................................................................................
Data Check Flow On Index_store_tag Operations177................................................................................................................................................................
Data Check Flow On Create_dirty Operations177................................................................................................................................................................
Data Check Flow On Hit_invalidate Operations178................................................................................................................................................................
Data Check Flow On Hit_writeback_invalidate Operations178................................................................................................................................................................
Data Check Flow On Fill Operations179................................................................................................................................................................
Data Check Flow On Hit_writeback Operations179................................................................................................................................................................
Writeback Flow180................................................................................................................................................................
Refill Flow180................................................................................................................................................................
Manipulation Of The Caches By An External Agent181................................................................................................................................................................
Writeback & Refill Flow181................................................................................................................................................................
Cpu Core Interrupts182................................................................................................................................................................
Non-maskable Interrupt (nmi)182................................................................................................................................................................
Ordinary Interrupts182................................................................................................................................................................
Software Interrupts Generated In Cpu Core182................................................................................................................................................................
Timer Interrupt182................................................................................................................................................................
Non-maskable Interrupt Signal182................................................................................................................................................................
Asserting Interrupts183................................................................................................................................................................
Hardware Interrupt Signals183................................................................................................................................................................
Masking Of Interrupt Request Signals184................................................................................................................................................................
Chapter 3 System Controller185................................................................................................................................................................
Overview185................................................................................................................................................................
Cpu Interface185................................................................................................................................................................
Ibus Interface185................................................................................................................................................................
Uart186................................................................................................................................................................
Eeprom186................................................................................................................................................................
Timer186................................................................................................................................................................
Interrupt Controller186................................................................................................................................................................
Dsu (deadman's Sw Unit)186................................................................................................................................................................
System Block Diagram187................................................................................................................................................................
Data Flow Diagram188................................................................................................................................................................
Registers189................................................................................................................................................................
Register Map189................................................................................................................................................................
S_gmr (general Mode Register)191................................................................................................................................................................
S_gsr (general Status Register)191................................................................................................................................................................
S_isr (interrupt Status Register)192................................................................................................................................................................
S_imr (interrupt Mask Register)193................................................................................................................................................................
S_nsr (nmi Status Register)194................................................................................................................................................................
S_ner (nmi Enable Register)195................................................................................................................................................................
S_ver (version Register)195................................................................................................................................................................
S_ior (io Port Register)196................................................................................................................................................................
S_wrcr (warm Reset Control Register)197................................................................................................................................................................
S_wrsr (warm Reset Status Register)198................................................................................................................................................................
S_pwcr (power Control Register)199................................................................................................................................................................
S_pwsr (power Status Register)200................................................................................................................................................................
Data Rate Control201................................................................................................................................................................
Burst Size Control201................................................................................................................................................................
Address Decoding201................................................................................................................................................................
Endian Conversion201................................................................................................................................................................
Endian Configuration Table202................................................................................................................................................................
Endian Translation Table In Endian Converter202................................................................................................................................................................
I/o Performance203................................................................................................................................................................
Memory Regions204................................................................................................................................................................
Memory Signal Connections205................................................................................................................................................................
External Pin Mapping205................................................................................................................................................................
Memory Performance206................................................................................................................................................................
Examples Of Memory Performance (4-word-burst Access From Cpu)206................................................................................................................................................................
Examples Of Memory Performance (4-word-burst Access From Ibus Master)206................................................................................................................................................................
Rmmdr (rom Mode Register)207................................................................................................................................................................
Rmatr (rom Access Timing Register)207................................................................................................................................................................
Sdmdr (sdram Mode Register)209................................................................................................................................................................
Sdtsr (sdram Type Selection Register)210................................................................................................................................................................
Sdptr (sdram Precharge Timing Register)211................................................................................................................................................................
Sdrmr (sdram Refresh Mode Register)211................................................................................................................................................................
Sdrcr (sdram Refresh Timer Count Register)212................................................................................................................................................................
Mbcr (memory Bus Control Register)212................................................................................................................................................................
Boot Rom213................................................................................................................................................................
Boot-rom Size Configuration At Reset213................................................................................................................................................................
Command Sequence214................................................................................................................................................................
Sdram216................................................................................................................................................................
Sdram Size Configuration At Reset216................................................................................................................................................................
Sdram Configurations Supported216................................................................................................................................................................
Sdram Word Order For Instruction-cache Line-fill217................................................................................................................................................................
Sdram Refresh219................................................................................................................................................................
Memory-to-cpu Prefetch Fifo219................................................................................................................................................................
Cpu-to-memory Write Fifo219................................................................................................................................................................
Sdram Memory Initialization220................................................................................................................................................................
Endian Conversion On Ibus Master221................................................................................................................................................................
Endian Translation Table For The Data Swap Mode (ibus Master)221................................................................................................................................................................
Endian Conversion On Ibus Slave222................................................................................................................................................................
Endian Translation Table For The Data Swap Mode (ibus Slave)222................................................................................................................................................................
Itcntr (ibus Timeout Timer Control Register)223................................................................................................................................................................
Itsetr (ibus Timeout Timer Set Register)223................................................................................................................................................................
Dsucntr (dsu Control Register)224................................................................................................................................................................
Dsusetr (dsu Time Set Register)224................................................................................................................................................................
Dsuclrr (dsu Clear Register)224................................................................................................................................................................
Dsutimr (dsu Elapsed Time Register)225................................................................................................................................................................
Dsu Register Setting Flow225................................................................................................................................................................
Endian Mode Software Issues226................................................................................................................................................................
Endian Modes226................................................................................................................................................................
Bit And Byte Order Of Endian Modes227................................................................................................................................................................
Half-word Data Array Example227................................................................................................................................................................
Word Data Array Example228................................................................................................................................................................
Chapter 4 Atm Cell Processor229................................................................................................................................................................
Function Features229................................................................................................................................................................
Atm Cell Processing Operation Overview232................................................................................................................................................................
Aal-5 Sublayer And Atm Layer232................................................................................................................................................................
Atm Cell234................................................................................................................................................................
Llc Encapsulation235................................................................................................................................................................
Memory Space236................................................................................................................................................................
Work Ram And Register Space237................................................................................................................................................................
Shared Memory237................................................................................................................................................................
Interruption237................................................................................................................................................................
Registers For Atm Cell Processing238................................................................................................................................................................
A_gmr (general Mode Register)240................................................................................................................................................................
A_gsr (general Status Register)240................................................................................................................................................................
A_imr (interrupt Mask Register)241................................................................................................................................................................
A_rqu (receiving Queue Underrun Register)242................................................................................................................................................................
A_rqa (receiving Queue Alert Register)242................................................................................................................................................................
A_ver (version Register)242................................................................................................................................................................
A_cmr (command Register)242................................................................................................................................................................
A_cer (command Extension Register)242................................................................................................................................................................
A_msa0 To A_msa3 (mailbox Start Address Register)243................................................................................................................................................................
A_mba0 To A_mba3 (mailbox Bottom Address Register)243................................................................................................................................................................
A_mta0 To A_mta3 (mailbox Tail Address Register)243................................................................................................................................................................
A_mwa0 To A_mwa3 (mailbox Write Address Register)244................................................................................................................................................................
A_rcc (valid Received Cell Counter)244................................................................................................................................................................
A_tcc (valid Transmitted Cell Counter)244................................................................................................................................................................
A_ruec (receive Unprovisioned Vpi/vci Error Cell Counter)244................................................................................................................................................................
A_ridc (receive Internal Dropped Cell Counter)244................................................................................................................................................................
A_t1r (t1 Time Register)245................................................................................................................................................................
A_tsr (time Stamp Register)245................................................................................................................................................................
A_ibbar (ibus Base Address Register)245................................................................................................................................................................
A_inbar (instruction Base Address Register)245................................................................................................................................................................
A_umcmd (utopia Management Interface Command Register)246................................................................................................................................................................
Data Structure247................................................................................................................................................................
Tx Buffer Structure247................................................................................................................................................................
Tx Packet247................................................................................................................................................................
Tx Buffer Elements248................................................................................................................................................................
Tx Packet Descriptor249................................................................................................................................................................
List Of Tx Packet Attribute249................................................................................................................................................................
Rx Pool Structure250................................................................................................................................................................
Tx Buffer Descriptor/link Pointer250................................................................................................................................................................
Rx Pool Descriptor/rx Buffer Directory/rx Buffer Descriptor/rx Link Pointer252................................................................................................................................................................
Rx Pool Descriptor253................................................................................................................................................................
List Of Rx Pool Attributes253................................................................................................................................................................
Rx Buffer Descriptor/ Link Pointer254................................................................................................................................................................
Initialization255................................................................................................................................................................
Before Starting Risc Core255................................................................................................................................................................
Transfer Of F/w255................................................................................................................................................................
After Risc Core's F/w Is Starting256................................................................................................................................................................
Instruction Ram And Instruction Cache256................................................................................................................................................................
Commands257................................................................................................................................................................
Set_link_rate Command258................................................................................................................................................................
Open_channel Command258................................................................................................................................................................
Open_channel Command And Indication258................................................................................................................................................................
Close_channel Command259................................................................................................................................................................
Close_channel Command And Indication259................................................................................................................................................................
Tx_ready Command260................................................................................................................................................................
Tx_ready Command And Indication260................................................................................................................................................................
Add_buffers Command261................................................................................................................................................................
Indirect_access Command262................................................................................................................................................................
Operations262................................................................................................................................................................
Work Ram Usage262................................................................................................................................................................
Transmission Function263................................................................................................................................................................
Structure Of The Transmit Queue265................................................................................................................................................................
Packet Info Structure265................................................................................................................................................................
Transmit Queue Packet Descriptor266................................................................................................................................................................
Tx Vc Table267................................................................................................................................................................
Raw Cell With Crc-10269................................................................................................................................................................
Send Indication Format269................................................................................................................................................................
Receiving Function270................................................................................................................................................................
Llc Encapsulation Format270................................................................................................................................................................
Receive Vc Table271................................................................................................................................................................
Raw Cell Data Format273................................................................................................................................................................
Receive Indication Format274................................................................................................................................................................
Reception Errors That Can Occur During Packet Reception275................................................................................................................................................................
Error Reporting Priorities275................................................................................................................................................................
Mailbox276................................................................................................................................................................
Mailbox Structure276................................................................................................................................................................
Chapter 5 Ethernet Controller277................................................................................................................................................................
Block Diagram Of Ethernet Controller Block277................................................................................................................................................................
Ethernet Controller's Register Categories279................................................................................................................................................................
Mac Control Register Map279................................................................................................................................................................
Statistics Counter Register Map281................................................................................................................................................................
Dma And Fifo Management Registers Map283................................................................................................................................................................
Interrupt And Configuration Registers Map284................................................................................................................................................................
En_ipgt (back-to-back Ipg Register)286................................................................................................................................................................
En_ipgr (non Back-to-back Ipg Register)286................................................................................................................................................................
En_clrt (collision Register)287................................................................................................................................................................
En_lmax (maximum Packet Length Register)287................................................................................................................................................................
En_retx (retry Count Register)287................................................................................................................................................................
En_ptvr (pause Timer Value Read Register)288................................................................................................................................................................
En_vltp (vlan Type Register)288................................................................................................................................................................
En_miic (mii Configuration Register)288................................................................................................................................................................
En_mcmd (mii Command Register)288................................................................................................................................................................
En_madr (mii Address Register)289................................................................................................................................................................
En_mwtd (mii Write Data Register)289................................................................................................................................................................
En_mrdd (mii Read Data Register)289................................................................................................................................................................
En_mind (mii Indicate Register)289................................................................................................................................................................
En_afr (address Filtering Register)290................................................................................................................................................................
En_ht1 (hash Table Register290................................................................................................................................................................
En_cam1 (carry Register 1 Mask Register)293................................................................................................................................................................
En_cam2 (carry Register 2 Mask Register)294................................................................................................................................................................
En_txcr (transmit Configuration Register)294................................................................................................................................................................
En_txfcr (transmit Fifo Control Register)295................................................................................................................................................................
Tx Fifo Control Mechanism295................................................................................................................................................................
En_txdpr (transmit Descriptor Pointer)296................................................................................................................................................................
En_rxcr (receive Configuration Register)296................................................................................................................................................................
En_rxfcr (receive Fifo Control Register)297................................................................................................................................................................
En_rxdpr (receive Descriptor Pointer)297................................................................................................................................................................
Rx Fifo Control Mechanism297................................................................................................................................................................
En_rxpdr (receive Pool Descriptor Pointer)298................................................................................................................................................................
En_ccr (configuration Register)298................................................................................................................................................................
En_isr (interrupt Serves Register)298................................................................................................................................................................
En_msr (mask Serves Register)299................................................................................................................................................................
Operation300................................................................................................................................................................
Buffer Structure For Ethernet Controller Block300................................................................................................................................................................
Buffer Structure For Ethernet Block300................................................................................................................................................................
Buffer Descriptor Format301................................................................................................................................................................
Transmit Descriptor Format301................................................................................................................................................................
Receive Descriptor Format301................................................................................................................................................................
Attribute For Transmit Descriptor301................................................................................................................................................................
Frame Transmission302................................................................................................................................................................
Attribute For Receive Descriptor302................................................................................................................................................................
Transmit Procedure304................................................................................................................................................................
Frame Reception305................................................................................................................................................................
Receive Procedure306................................................................................................................................................................
Address Filtering307................................................................................................................................................................
Chapter 6 Usb Controller309................................................................................................................................................................
Internal Block Diagram310................................................................................................................................................................
Usb Controller Internal Configuration310................................................................................................................................................................
U_gmr (usb General Mode Register)313................................................................................................................................................................
U_ver (usb Frame Number/version Register)313................................................................................................................................................................
U_ep0cr (usb Ep0 Control Register)320................................................................................................................................................................
U_ep1cr (usb Ep1 Control Register)321................................................................................................................................................................
U_ep2cr (usb Ep2 Control Register)321................................................................................................................................................................
U_ep3cr (usb Ep3 Control Register)322................................................................................................................................................................
U_ep4cr (usb Ep4 Control Register)323................................................................................................................................................................
U_ep5cr (usb Ep5 Control Register)324................................................................................................................................................................
U_ep6cr (usb Ep6 Control Register)324................................................................................................................................................................
U_cmr (usb Command Register)325................................................................................................................................................................
U_ca (usb Command Extension Register)325................................................................................................................................................................
U_tepsr (usb Tx Endpoint Status Register)326................................................................................................................................................................
U_rp0ir (usb Rx Pool0 Information Register)326................................................................................................................................................................
U_rp0ar (usb Rx Pool0 Address Register)327................................................................................................................................................................
U_rp1ir (usb Rx Pool1 Information Register)327................................................................................................................................................................
U_rp1ar (usb Rx Pool1 Address Register)327................................................................................................................................................................
U_rp2ir (usb Rx Pool2 Information Register)328................................................................................................................................................................
U_rp2ar (usb Rx Pool2 Address Register)328................................................................................................................................................................
U_tmsa (usb Tx Mailbox Start Address Register)328................................................................................................................................................................
U_tmba (usb Tx Mailbox Bottom Address Register)328................................................................................................................................................................
U_tmra (usb Tx Mailbox Read Address Register)328................................................................................................................................................................
U_tmwa (usb Tx Mailbox Write Address Register)329................................................................................................................................................................
U_rmsa (usb Rx Mailbox Start Address Register)329................................................................................................................................................................
U_rmba (usb Rx Mailbox Bottom Address Register)329................................................................................................................................................................
U_rmra (usb Rx Mailbox Read Address Register)329................................................................................................................................................................
U_rmwa (usb Rx Mailbox Write Address Register)329................................................................................................................................................................
Usb Attachment Sequence330................................................................................................................................................................
Receive Pool Settings332................................................................................................................................................................
Transmit/receive Mailbox Settings332................................................................................................................................................................
Mailbox Configuration333................................................................................................................................................................
Data Transmit Function334................................................................................................................................................................
Overview Of Transmit Processing334................................................................................................................................................................
Tx Buffer Configuration334................................................................................................................................................................
Division Of Data Into Usb Packets334................................................................................................................................................................
Configuration Of Transmit Buffer Directory336................................................................................................................................................................
Data Transmit Modes337................................................................................................................................................................
Transmit Command Issue339................................................................................................................................................................
Transmit Status Register340................................................................................................................................................................
Usb Controller Processing At Data Transmitting341................................................................................................................................................................
Usb Controller Transmit Operation Flow Chart341................................................................................................................................................................
Tx Indication343................................................................................................................................................................
Transmit Indication Format343................................................................................................................................................................
Data Receive Function344................................................................................................................................................................
Overview Of Receive Processing344................................................................................................................................................................
Rx Buffer Configuration345................................................................................................................................................................
Receive Buffer Configuration345................................................................................................................................................................
Receive Descriptor Configuration346................................................................................................................................................................
Buffer Directory Addition Command347................................................................................................................................................................
Data Receive Mode348................................................................................................................................................................
Data Receiving In Endpoint0, Endpoint6349................................................................................................................................................................
Endpoint2, Endpoint4 Receive Normal Mode349................................................................................................................................................................
Endpoint2, Endpoint4 Receive Assemble Mode350................................................................................................................................................................
Endpoint2, Endpoint4 Receive Separate Mode350................................................................................................................................................................
Usb Controller Receive Processing352................................................................................................................................................................
Usb Controller Receive Operations (normal Mode)352................................................................................................................................................................
Usb Controller Receive Operations (assemble Mode)354................................................................................................................................................................
Usb Controller Receive Operation Sequence (separate Mode)356................................................................................................................................................................
Detection Of Errors On Usb358................................................................................................................................................................
Usb Timing Errors358................................................................................................................................................................
Rx Data Corruption On Isochronous Endpoint360................................................................................................................................................................
Rx Fifo Overrun361................................................................................................................................................................
Example Of Buffers Including Corrupted Data361................................................................................................................................................................
Rx Indication362................................................................................................................................................................
Power Management364................................................................................................................................................................
Suspend364................................................................................................................................................................
Suspend Sequence364................................................................................................................................................................
Resume365................................................................................................................................................................
Resume Sequence365................................................................................................................................................................
Remote Wake Up366................................................................................................................................................................
Remote Wake Up Sequence366................................................................................................................................................................
Receiving Sof Packet367................................................................................................................................................................
Receiving Sof Packet And Updating The Frame Number367................................................................................................................................................................
Updating Frame Number Automatically367................................................................................................................................................................
Checking If The Skew Of Sof Arrival Time Is Allowable Of Not367................................................................................................................................................................
Allowable Skew For Sof367................................................................................................................................................................
Loopback Mode368................................................................................................................................................................
Data Flow In Loopback Mode368................................................................................................................................................................
Example Of Connection369................................................................................................................................................................
Chapter 7 Pci Controller370................................................................................................................................................................
The Pci Controller Block Diagram370................................................................................................................................................................
Bus Bridge Functions371................................................................................................................................................................
Internal Bus To Pci Transaction371................................................................................................................................................................
Posted Write Transaction From Internal Bus To Pci372................................................................................................................................................................
Non Posted Write Transaction From Internal Bus To Pci373................................................................................................................................................................
Delayed Read Transaction From Internal Bus To Pci374................................................................................................................................................................
Non Delayed Read Transaction From Internal Bus To Pci375................................................................................................................................................................
Pci To Internal Bus Transaction376................................................................................................................................................................
Posted Write Transaction From Pci To Internal Bus377................................................................................................................................................................
Non Posted Write Transaction From Pci To Internal Bus378................................................................................................................................................................
Delayed Read Transaction From Pci To Internal Bus379................................................................................................................................................................
Non Delayed Read Transaction From Pci To Internal Bus380................................................................................................................................................................
Abnormal Termination381................................................................................................................................................................
Warning For Deadlocks382................................................................................................................................................................
Pci Power Management Interface383................................................................................................................................................................
Power State383................................................................................................................................................................
Power Management Event383................................................................................................................................................................
Power State Transition384................................................................................................................................................................
The Sequence Of The Transition By Issues From Pci-host384................................................................................................................................................................
The Sequence Of The Transition By Pme385................................................................................................................................................................
Functions In Host-mode386................................................................................................................................................................
Generating Configuration Cycle386................................................................................................................................................................
The Content Of P_pcar Register For Type0 Configuration Cycle386................................................................................................................................................................
The Content Of P_pcar Register For Type1 Configuration Cycle386................................................................................................................................................................
Device Number Decode Table387................................................................................................................................................................
Pci Bus Arbiter388................................................................................................................................................................
An Example How To Connect Ad [31:16] Signal Line To Idsel Port388................................................................................................................................................................
Address Stepping For Idsel388................................................................................................................................................................
Reset Output389................................................................................................................................................................
Interrupt Input389................................................................................................................................................................
Arbitration In Alternating Mode389................................................................................................................................................................
Arbitration In Rotating Mode389................................................................................................................................................................
P_plba (pci Lower Base Address Register)391................................................................................................................................................................
P_ibba (internal Bus Base Address Register)391................................................................................................................................................................
P_verr (version Register)391................................................................................................................................................................
P_pcar (pci Configuration Address Register)392................................................................................................................................................................
P_pcdr (pci Configuration Data Register)392................................................................................................................................................................
P_igsr (internal Bus-side General Status Register)393................................................................................................................................................................
P_iimr (internal Bus Interrupt Mask Register)394................................................................................................................................................................
P_pgsr (pci-side General Status Register)395................................................................................................................................................................
P_pimr (pci Interrupt Mask Register)397................................................................................................................................................................
P_hmcr (host Mode Control Register)398................................................................................................................................................................
P_pcdr (power Consumption Data Register)398................................................................................................................................................................
P_pddr (power Dissipation Data Register)398................................................................................................................................................................
P_bcnt (bridge Control Register)399................................................................................................................................................................
P_ppcr (pci Power Control Register)400................................................................................................................................................................
P_swrr (software Reset Register)400................................................................................................................................................................
P_rtmr (retry Timer Register)401................................................................................................................................................................
P_config (pci Configuration Registers)401................................................................................................................................................................
Information For Software411................................................................................................................................................................
Nic Mode411................................................................................................................................................................
Host Mode412................................................................................................................................................................
Chapter 8 Uart414................................................................................................................................................................
Uart Block Diagram414................................................................................................................................................................
Uartrbr (uart Receiver Data Buffer Register)416................................................................................................................................................................
Uartthr (uart Transmitter Data Holding Register)416................................................................................................................................................................
Uartier (uart Interrupt Enable Register)416................................................................................................................................................................
Uartdll (uart Divisor Latch Lsb Register)416................................................................................................................................................................
Uartdlm (uart Divisor Latch Msb Register)417................................................................................................................................................................
Correspondence Between Baud Rates And Divisors417................................................................................................................................................................
Uartiir (uart Interrupt Id Register)418................................................................................................................................................................
Uartfcr (uart Fifo Control Register)419................................................................................................................................................................
Uartlcr (uart Line Control Register)420................................................................................................................................................................
Uartmcr (uart Modem Control Register)421................................................................................................................................................................
Uartlsr (uart Line Status Register)422................................................................................................................................................................
Uartmsr (uart Modem Status Register)423................................................................................................................................................................
Uartscr (uart Scratch Register)423................................................................................................................................................................
Chapter 9 Timer424................................................................................................................................................................
Block Diagram424................................................................................................................................................................
Tmmr (timer Mode Register)425................................................................................................................................................................
Tm0csr (timer Ch0 Count Set Register)426................................................................................................................................................................
Tm1csr (timer Ch1 Count Set Register)426................................................................................................................................................................
Tm0ccr (timer Ch0 Current Count Register)426................................................................................................................................................................
Tm1ccr (timer Ch1 Current Count Register)426................................................................................................................................................................
Chapter 10 Micro Wire427................................................................................................................................................................
Data Read At The Power Up Load428................................................................................................................................................................
Accessing To Eeprom428................................................................................................................................................................
Eeprom Initial Data428................................................................................................................................................................
Eeprom Command List428................................................................................................................................................................
Eccr (eeprom Command Control Register)429................................................................................................................................................................
Erdr (eeprom Read Data Register)429................................................................................................................................................................
Appendix A Mips Iii Instruction Set Details431................................................................................................................................................................
A.1 Instruction Notation Conventions431................................................................................................................................................................
A-1 Cpu Instruction Operation Notations432................................................................................................................................................................
A.2 Load And Store Instructions433................................................................................................................................................................
A-2 Load And Store Common Functions433................................................................................................................................................................
A.3 Jump And Branch Instructions434................................................................................................................................................................
A-3 Access Type Specifications For Loads/stores434................................................................................................................................................................
A.4 System Control Coprocessor (cp0) Instructions435................................................................................................................................................................
A.5 Cpu Instruction435................................................................................................................................................................
A.6 Cpu Instruction Opcode Bit Encoding588................................................................................................................................................................
B-2 Calculation Example Of Cp0 Hazard And Number Of Instructions Inserted594................................................................................................................................................................

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