Table of Contents
Advertisement
(10) Instruction Fetch
Source:
The confirmation of the operating mode and TLB necessary for instruction fetch.
Examples 1.
When changing the operating mode from User to Kernel and fetching instructions after the
KSU, EXL, and ERL bits of the Status register are modified.
2.
When fetching instructions using the modified TLB entry after TLB modification.
(11) Instruction Fetch Exception
Destination:
The completion of writing to registers containing information related to the exception when an
exception occurs on instruction fetch.
(12) Interrupts
Source:
The confirmation of registers judging the condition of occurrence of interrupt when an
interrupt factor is detected.
(13) Loads/Sores
Source:
The confirmation of the operating mode related to the address generation of Load/Store
instructions, TLB entries, the cache mode set in the K0 bit of the Config register, and the
registers setting the condition of occurrence of a Watch exception.
Example
When Loads/Stores are executed in the kernel field after changing the mode from User to
Kernel.
(14) Load/Store Exception
Destination:
The completion of writing to registers containing information related to the exception when an
exception occurs on load or store operation.
(15) TLB Shutdown
Destination:
The completion of writing to the TS bit of the Status register when a TLB shutdown occurs.
APPENDIX B V
4120A COPROCESSOR 0 HAZARDS
R
Preliminary User's Manual S15543EJ1V0UM
593
Advertisement
Table of Contents
