Page 1 Preliminary User’s Manual µ µ µ µ PD98502 Network Controller Document No. S15543EJ1V0UM00 (1st edition) Date Published December 2001 NS CP(K) 2001 Printed in Japan...
Page 2 [MEMO] Preliminary User’s Manual S15543EJ1V0UM...
Page 3 SUMMARY OF CONTENTS CHAPTER 1 INTRODUCTION ........................23 CHAPTER 2 V 4120A ..........................57 CHAPTER 3 SYSTEM CONTROLLER ....................185 CHAPTER 4 ATM CELL PROCESSOR....................229 CHAPTER 5 ETHERNET CONTROLLER....................277 CHAPTER 6 USB CONTROLLER ......................309 CHAPTER 7 PCI CONTROLLER ......................370 CHAPTER 8 UART ..........................
Page 4 NOTES FOR CMOS DEVICES PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred.
Page 5 The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact an NEC sales representative in advance.
Page 6 PREFACE Readers This manual is intended for engineers who need to be familiar with the capability of the µ PD98502 in order to develop application systems based on it. Purpose The purpose of this manual is to help users understand the hardware capabilities (listed below) of the µ...
Page 7: Table Of Contents
CONTENTS CHAPTER 1 INTRODUCTION ....................... 23 Features ............................23 Ordering Information ......................... 23 System Configuration........................ 24 Block Diagram (Summary) ......................25 Block Diagram (Detail)....................... 26 1.5.1 4120A RISC processor core ......................26 1.5.2 IBUS ..............................27 1.5.3 System controller ...........................28 1.5.4 ATM cell processor ........................29 1.5.5 Ethernet controller .........................30 1.5.6...
Page 8 2.1.6 Floating-point unit (FPU)........................64 2.1.7 CPU core memory management system (MMU) ................65 2.1.8 Translation lookaside buffer (TLB) ....................65 2.1.9 Operating modes ...........................65 2.1.10 Cache ............................65 2.1.11 Instruction pipeline .........................66 MIPS III Instruction Set Summary.....................66 2.2.1 MIPS III ISA instruction formats .....................66 2.2.2 Instruction classes .........................67 Pipeline............................84...
Page 9 CHAPTER 3 SYSTEM CONTROLLER....................185 Overview ........................... 185 3.1.1 CPU interface ..........................185 3.1.2 Memory interface .........................185 3.1.3 IBUS Interface ..........................185 3.1.4 UART............................186 3.1.5 EEPROM .............................186 3.1.6 Timer ............................186 3.1.7 Interrupt controller ........................186 3.1.8 DSU (Deadman’s SW Unit) ......................186 3.1.9 System block diagram .........................187 3.1.10 Data flow diagram........................188 Registers...........................
Page 10 3.4.15 SDRAM refresh..........................219 3.4.16 Memory-to-CPU prefetch FIFO ....................219 3.4.17 CPU-to-memory write FIFO ......................219 3.4.18 SDRAM memory initialization ......................220 IBUS Interface...........................221 3.5.1 Overview............................221 3.5.2 Endian Conversion on IBUS master ....................221 3.5.3 Endian Conversion on IBUS slave ....................222 3.5.4 ITCNTR (IBUS Timeout Timer Control Register) .................223 3.5.5 ITSETR (IBUS Timeout Timer Set Register)................223 DSU (Deadman’s SW Unit) ......................224...
Page 11 4.4.18 A_T1R (T1 Time Register)......................245 4.4.19 A_TSR (Time Stamp Register) ....................245 4.4.20 A_IBBAR (IBUS Base Address Register) ..................245 4.4.21 A_INBAR (Instruction Base Address Register)................245 4.4.22 A_UMCMD (UTOPIA Management Interface Command Register) ..........246 Data Structure .......................... 247 4.5.1 Tx buffer structure ........................247 4.5.2 Rx pool structure .........................250 Initialization ..........................
Page 12 5.2.20 En_HT1 (Hash Table Register 1)....................290 5.2.21 En_HT2 (Hash Table Register 2)....................290 5.2.22 En_CAR1 (Carry Register 1) .......................291 5.2.23 En_CAR2 (Carry Register 2) .......................292 5.2.24 En_CAM1 (Carry Register 1 Mask Register) ................293 5.2.25 En_CAM2 (Carry Register 2 Mask Register) ................294 5.2.26 En_TXCR (Transmit Configuration Register)................294 5.2.27 En_TXFCR (Transmit FIFO Control Register) ................295 5.2.28 En_TXDPR (Transmit Descriptor Pointer) ...................296...
Page 13 6.2.20 U_RP1IR (USB Rx Pool1 Information Register) ................327 6.2.21 U_RP1AR (USB Rx Pool1 Address Register) ................327 6.2.22 U_RP2IR (USB Rx Pool2 Information Register) ................328 6.2.23 U_RP2AR (USB Rx Pool2 Address Register) ................328 6.2.24 U_TMSA (USB Tx MailBox Start Address Register)..............328 6.2.25 U_TMBA (USB Tx MailBox Bottom Address Register) ..............328 6.2.26 U_TMRA (USB Tx MailBox Read Address Register)..............328 6.2.27 U_TMWA (USB Tx MailBox Write Address Register) ..............329...
Page 14 CHAPTER 7 PCI CONTROLLER ......................370 Overview ...........................370 Bus Bridge Functions......................371 7.2.1 Internal bus to PCI transaction.....................371 7.2.2 PCI to internal bus transaction.....................376 7.2.3 Abnormal Termination........................381 7.2.4 Warning for Deadlocks.........................382 PCI Power Management Interface ..................383 7.3.1 Power state..........................383 7.3.2 Power management event ......................383 7.3.3 Power supply ..........................383 7.3.4...
Page 15 8.3.4 UARTIER (UART Interrupt Enable Register) ................416 8.3.5 UARTDLL (UART Divisor Latch LSB Register) ................416 8.3.6 UARTDLM (UART Divisor Latch MSB Register) .................417 8.3.7 UARTIIR (UART Interrupt ID Register) ..................418 8.3.8 UARTFCR (UART FIFO Control Register) ..................419 8.3.9 UARTLCR (UART Line Control Register) ..................420 8.3.10 UARTMCR (UART Modem Control Register)................421 8.3.11 UARTLSR (UART Line Status Register)..................422 8.3.12 UARTMSR (UART Modem Status Register) ................423...
Page 16 LIST OF FIGURES (1/5) Figure No. Title Page Examples of the µ PD98502 System Configuration ..................24 Block Diagram of the µ PD98502........................25 Block Diagram of V 4120A RISC Processor....................26 Block Diagram of IBUS ..........................27 Block Diagram of System Controller ......................28 Block Diagram of ATM Cell Processor......................29 Block Diagram of Ethernet Controller......................30 Block Diagram of USB Controller........................31...
Page 17 LIST OF FIGURES (2/5) Figure No. Title Page 2-29 Supervisor Mode Address Space ........................108 2-30 Kernel Mode Address Space ........................111 µ PD98502 Physical Address Space ......................116 2-31 2-32 CP0 Registers and TLB ..........................117 2-33 Format of a TLB Entry ..........................118 2-34 Index Register..............................119 2-35...
Page 18 LIST OF FIGURES (3/5) Figure No. Title Page 2-71 Instruction Cache State Diagram .........................173 2-72 Data Check Flow on Instruction Fetch ......................174 2-73 Data Check Flow on Load Operations ......................174 2-74 Data Check Flow on Store Operations......................175 2-75 Data Check Flow on Index_Invalidate Operations ..................175 2-76 Data Check Flow on Index_Writeback_Invalidate Operations ..............176 2-77...
Page 19 LIST OF FIGURES (4/5) Figure No. Title Page 4-19 Open_Channel Command and Indication....................258 4-20 Close_Channel Command and Indication ....................259 4-21 Tx_Ready Command and Indication......................260 4-22 Add_Buffers Command ..........................261 4-23 Indirect_Access Command ..........................262 4-24 Work RAM Usage ............................263 4-25 Structure of the Transmit Queue........................265 4-26 Packet Info Structure ...........................265 4-27...
Page 20 LIST OF FIGURES (5/5) Figure No. Title Page 6-16 Data Receiving in EndPoint0, EndPoint6 .....................349 6-17 EndPoint2, EndPoint4 Receive Normal Mode....................349 6-18 EndPoint2, EndPoint4 Receive Assemble Mode ..................350 6-19 EndPoint2, EndPoint4 Receive Separate Mode...................350 6-20 4120A Receive Processing........................351 6-21 USB Controller Receive Operations (Normal Mode)..................352 6-22 USB Controller Receive Operations (Assemble Mode)................354 6-23...
Page 21 LIST OF TABLES (1/2) Table No. Title Page System Control Coprocessor (CP0) Register Definitions................64 Number of Delay Slot Cycles Necessary for Load and Store Instructions .............67 Byte Specification Related to Load and Store Instructions ................68 Load/Store Instruction............................69 Load/Store Instruction (Extended ISA) ......................70 ALU Immediate Instruction ..........................71 ALU Immediate Instruction (Extended ISA) ....................72 Three-Operand Type Instruction........................72...
Page 22 LIST OF TABLES (2/2) Table No. Title Page Endian Configuration Table..........................202 Endian Translation Table in Endian Converter.....................202 External Pin Mapping...........................205 Examples of Memory Performance (4-word-burst access from CPU)............206 Examples of Memory Performance (4-word-burst access from IBUS Master) ..........206 Boot-ROM Size Configuration at Reset .......................213 Command Sequence ...........................214 SDRAM Size Configuration at Reset ......................216 SDRAM Configurations Supported ......................216...
Page 23: Chapter 1 Introduction
CHAPTER 1 INTRODUCTION The µ PD98502 is a high performance controller, which can perform the protocol conversion between IP Packets and ATM Cells, which is especially suitable for ADSL router. It includes high performance MIPS based 64-bit RISC processor V 4120A CPU core, ATM Cell Processor, Ethernet Controller, USB Controller Block, PCI Controller Block, UTOPIA2 interface and SDRAM interface.
Page 24: System Configuration
CHAPTER 1 INTRODUCTION 1.3 System Configuration The µ PD98502 can perform bridging and routing function between ADSL/ATM interface and USB/Ethernet interface and provides this function in a single chip. By selecting user interface, examples of system configuration will be realized as shown below. USB and Ethernet functions will exclusively operate each other. Figure 1-1.
Page 25: Block Diagram (Summary)
CHAPTER 1 INTRODUCTION 1.4 Block Diagram (Summary) Figure 1-2. Block Diagram of the µ µ µ µ PD98502 IBUS 4120A RISC Processor Core Full-Speed USB Controller PROM/Flash SDRAM 3.3V MII Ethernet Controller #1, #2 System Controller RS-232C/ 16.5/25/33 MHz Micro Wire UTOPIA 2 Parallel Port ATM Cell...
Page 26: Block Diagram (Detail)
CHAPTER 1 INTRODUCTION 1.5 Block Diagram (Detail) 1.5.1 V 4120A RISC processor core We will support real-time OS running on high performance RISC processor V 4120A core and can perform network protocols (TCP/IP, PPP, SNMP, HTTP etc) to realize ADSL router and modem. Middleware including RTOS will be loaded to SDRAM from external PROM and Flash ROM and by setting write protected area for such an area, high speed processing will be realized together with large size instruction cache.
Page 27: Ibus
CHAPTER 1 INTRODUCTION 1.5.2 IBUS The IBUS is a 32-bit, 66-MHz high-speed on-chip bus, which enables interconnection each controller blocks. The IBUS supports the following bus protocols; • Single read/write transfer • Burst read/write transfer • Slave lock • Retry and disconnect •...
Page 28: System Controller
1.5.3 System controller System Controller is µ PD98502’s internal system controller. System Controller provides bridging function among the V 4120A System Bus “SysAD”, NEC original high-speed on-chip bus “IBUS” and memory bus for SDRAM/PROM/Flash. Features of System Controller are as follows;...
Page 29: Atm Cell Processor
CHAPTER 1 INTRODUCTION 1.5.4 ATM cell processor By using NEC proprietary 32-bit controller, we will realize ATM Cell processor Unit. ATM Cell processing by firmware realizes more flexibility than before. Features of ATM Cell Processor are as follows; • Realize software SAR function by using 32-bit RISC controller (76 MIPS @66 MHz) •...
Page 30: Ethernet Controller
CHAPTER 1 INTRODUCTION 1.5.5 Ethernet controller Ethernet Controller supports 2-channel 10 Mbps/100 Mbps Ethernet MAC (Media Access Control) function and MII (Media Independent Interface) function. Features of Ethernet Controller are as follows; • Supports 10 M/100 M Ethernet MAC function compliant to IEEE802.3 and IEEE802.3u •...
Page 31: Usb Controller
CHAPTER 1 INTRODUCTION 1.5.6 USB controller USB Controller provides Full Speed Function device function defined in Universal Serial Bus. Features of USB Controller are as follows; • Compliant to Universal Serial Bus Specification Rev. 1.1 • Supports Device class function by software running on V 4120A •...
Page 32: Pci Controller
CHAPTER 1 INTRODUCTION 1.5.7 PCI controller PCI Controller provides PCI Bus function defined by PCI SIG. This block is bridging between IBUS and PCI. Features of PCI Controller are as follows; • 32-bit PCI Interface (up to 33 MHz) • 32-bit IBUS Interface (up to 33 MHz) •...
Page 33: Pin Configuration (Bottom View)
CHAPTER 1 INTRODUCTION 1.6 Pin Configuration (Bottom View) • 500-pin Tape BGA (Heat spread type) (40 × 40) µ PD98502N7-H6 Index Mark Y W V U T R P N M L K J H G F E D C B A AK AJ AH AG AF AE AD AC AB AA Preliminary User’s Manual S15543EJ1V0UM...
Page 34 CHAPTER 1 INTRODUCTION Pin Name (1/3) Pin No. Pin Name Pin No. Pin Name Pin No. Pin Name Pin No. Pin Name Pin No. Pin Name SMA13 URSDO NJTRST PGTO2_B SMD0 RMSL1 IC-OPEN PRQI1_B SMD4 MWDO PAD0 PAD5 SMD7 POM3 PAD6 SMD19 POM5...
Page 35 CHAPTER 1 INTRODUCTION (2/3) Pin No. Pin Name Pin No. Pin Name Pin No. Pin Name Pin No. Pin Name Pin No. Pin Name IVDD IC-PUp MICRS IVDD IC-PDn MIMCLK PAD14 IVDD PAD26 EVDD MITD3 PAD15 PAD16 PAD25 AB26 EVDD EVDD PAD17 PAD24...
Page 36 CHAPTER 1 INTRODUCTION (3/3) Pin No. Pin Name Pin No. Pin Name Pin No. Pin Name Pin No. Pin Name Pin No. Pin Name AG11 UDRD0 MICOL AH25 EVDD AJ17 UDTD5 UDRD5 AG12 IVDD MI2RD0 AH26 IVDD AJ18 AK10 UDRD2 AG13 UDRAD1 MI2MD...
Page 37: Pin Function
CHAPTER 1 INTRODUCTION 1.7 Pin Function Symbol of I/O column indicates following status in this section. : Input : Output I/O : Bidirection I/OZ : Bidirection (Include Hi-Z state) I/OD : Bidirection (Open drain output) OZ : Output (Include Hi-Z state) OD : Output (Open drain) 1.7.1 Power supply Pin Name...
Page 38: System Control Interface
CHAPTER 1 INTRODUCTION 1.7.4 System control interface Pin Name Pin No. Active Level Function SCLK System clock (33 MHz) CLKSL Clock select (100 MHz/66 MHz) PSMD System PLL mode control (0: normal, 1: through) PSTBY System PLL standby mode control (0: active, 1: standby) PUMD USB PLL mode control (0: normal, 1: through) PUSTBY...
Page 39: Memory Interface
CHAPTER 1 INTRODUCTION 1.7.5 Memory interface (1/2) Pin Name Pin No. Active Level Function SDCLK0 SDRAM clock SDCLK1 SDRAM clock SDCKE0 SDRAM clock enable SDCKE1 SDRAM clock enable SDCS_B Chip select SDRAS_B Row address strobe SDCAS_B Column address strobe SDWE_B Write enable SRMCS_B PROM/FLASH chip select...
Page 40 CHAPTER 1 INTRODUCTION (2/2) Pin Name Pin No. Active Level Function SMD11 Memory data SMD12 Memory data SMD13 Memory data SMD14 Memory data SMD15 Memory data SMD16 Memory data SMD17 Memory data SMD18 Memory data SMD19 Memory data SMD20 Memory data SMD21 Memory data SMD22...
Page 41: Pci Interface
CHAPTER 1 INTRODUCTION 1.7.6 PCI interface (1/2) Pin Name Pin No. Active Level Function PSCLK PCI clock PARBN PCI arbiter enable PMODE PCI mode select (L: host, H: NIC) PIDSEL Initialization device select PDSEL_B I/OZ Device select PER_B I/OZ Parity error PFRA_B I/OZ Cycle frame...
Page 42 CHAPTER 1 INTRODUCTION (2/2) Pin Name Pin No. Active Level Function PAD11 I/OZ PCI address and data PAD12 I/OZ PCI address and data PAD13 I/OZ PCI address and data PAD14 I/OZ PCI address and data PAD15 I/OZ PCI address and data PAD16 I/OZ PCI address and data...
Page 43: Atm Interface
CHAPTER 1 INTRODUCTION 1.7.7 ATM interface 1.7.7.1 UTOPIA management interface Pin Name Pin No. Active Level Function UMMD AG20 Management mode select UMINT_B AH19 Interrupt from PHY UMRD_B AK21 Management read enable UMRDY_B AJ19 Management data ready UMRST_B AK20 PHY reset UMSL_B AH20 PHY select...
Page 44 CHAPTER 1 INTRODUCTION 1.7.7.2 UTOPIA data interface Pin Name Pin No. Active Level Function CLKUSL0 UTOPIA clock select CLKUSL1 (CLKUSL1/0 = L/L: 33 MHz, H/L: 25 MHz, L/H: 16.5 MHz) UDRCLK AK11 Receive clock UDRCLV Receive cell available UDRE_B Receive enable UDRSC Receive cell start UDRAD0...
Page 45: Ethernet Interface
CHAPTER 1 INTRODUCTION 1.7.8 Ethernet interface 1.7.8.1 Ethernet interface (Channel 1) Pin Name Pin No. Active Level Function MIMCLK MII management clock MIMD MII management MICOL Collision MICRS Carrier sense MIRCLK Receive clock (2.5/25 MHz) MIRDV Receive data valid MIRER Receive error MIRD0 Receive data...
Page 46: Usb Interface
CHAPTER 1 INTRODUCTION 1.7.8.2 Ethernet interface (Channel 2) Pin Name Pin No. Active Level Function MI2MCLK MII management clock MI2MD MII management MI2COL Collision MI2CRS Carrier sense MI2RCLK Receive clock (2.5/25 MHz) MI2RDV Receive data valid MI2RER Receive error MI2RD0 Receive data MI2RD1 Receive data...
Page 47: Uart Interface
CHAPTER 1 INTRODUCTION 1.7.10 UART interface Pin Name Pin No. Active Level Function URCLK UART external clock URCTS_B UART clear to send URDCD_B UART data carrier detect URDSR_B UART data set ready URDTR_B UART data terminal ready URRTS_B UART data request to send URSDI UART serial data input URSDO...
Page 48: Open
CHAPTER 1 INTRODUCTION 1.7.14 I.C. – open Pin Name Pin No. Active Level Function IC-OPEN A17, A19, A20, A28, B16, B17, B18, B19, B26, C20, C24, D18, D20, E18, Y1, AA1, AB1, AB27, AB28, AC28, AC29, AD29, AH12, AJ12 1.7.15 I.C.– pull down Pin Name Pin No.
Page 49: I/O Register Map
CHAPTER 1 INTRODUCTION 1.8 I/O Register Map Core Offset Register Name Access by Description Length 4120A (Byte) F000H A_GMR General Mode Register F004H A_GSR General Status Register F008H A_IMR Interrupt Mask Register F00CH A_RQU Receive Queue Underrunning F010H A_RQA Receive Queue Alert F014H Reserved for future use F018H...
Page 50 CHAPTER 1 INTRODUCTION Core Offset Register Name Access by Description Length 4120A (Byte) 048H-04CH Reserved for future use 050H P_BCNT Bridge Control Register 054H P_PPCR Power Control Register 058H P_SWRR Software Reset Register 05CH P_PTMR Retry Timer Register 060H-0FFH Reserved for future use 100H-1FFH P_CONFIG Configuration Registers.
Page 51 CHAPTER 1 INTRODUCTION Core Offset Register Name Access by Description Length 4120A (Byte) Ether 1D0H En_TBCA Transmit Broadcast Packet Counter Ether 1D4H En_TUCA Transmit Unicast Packet Counter Ether 1D8H En_TXPF Transmit PAUSE control Frame Counter Ether 1DCH En_TDFR Transmit Single Deferral Packet Counter Ether 1E0H En_TXDF...
Page 52 CHAPTER 1 INTRODUCTION Core Offset Register Name Access by Description Length 4120A (Byte) SYSCNT MACAR1 MAC Address Register 1 SYSCNT MACAR2 MAC Address Register 2 SYSCNT MACAR3 MAC Address Register 3 SYSCNT E4H-FFH Reserved for future use SYSCNT 100H RMMDR Boot ROM Mode Register SYSCNT 104H...
Page 53: Memory Map
CHAPTER 1 INTRODUCTION 1.9 Memory Map Using a 32-bit address, the processor physical address space encompasses 4 Gbytes. V 4120A uses this 4-Gbyte physical address space as shown in the following figure. Figure 1-10. Memory Map FFFF_FFFFH M irror of 0000_0000H - 1FFF_FFFF 2000_0000H 1FFF_FFFFH...
Page 54: Reset Configuration
CHAPTER 1 INTRODUCTION 1.10 Reset Configuration The falling edge of Clock Control Unit (CCU)’s reset line (RST_B) serves as the µ PD98502's internal reset. The System Controller generates the IBUS reset signal using RST_B for the global reset of the µ PD98502. After 4 IBUS clock (SDCLK), the System Controller deasserts the IBUS reset signal synchronously with IBUS clock (66 MHz).
Page 55: Interrupts
CHAPTER 1 INTRODUCTION 1.11 Interrupts The controller supports maskable interrupts and Non-Maskable to the CPU. Figure 1-12. Interrupt Signal Connection 4 1 2 0 A S ys te m C o n tro lle r E X T N M I n m ib S _ N S R B U S -IF...
Page 56: Clock Control Unit
CHAPTER 1 INTRODUCTION 1.12 Clock Control Unit This section describe µ PD98502’s internal clock is supplied by Clock Control Unit (CCU) with following figure. Figure 1-13. Block Diagram of Clock Control Unit C C U (C L O C K C O N T R O L U N IT ) 33/25/16.5 M H z 66 M H z C L O C K...
Page 57: Chapter 2 4120A
CHAPTER 2 V 4120A The µ µ µ µ PD98502 doesn’t support MIPS16 instructions. Caution This chapter describes an V 4120A RISC Processor Core operation (MIPS instruction, Pipeline, etc.). Following in this Document, it is call for V 4120A RISC Processor Core with “V 4120A”...
Page 58: Internal Block Configuration
CHAPTER 2 V 4120A 2.1.1 Internal block configuration 2.1.1.1 CPU CPU has hardware resources to process an integer instruction. They are the 64-bit register file, 64-bit integer data bus, and multiply-and-accumulate operation unit. 2.1.1.2 Coprocessor 0 (CP0) CP0 incorporates a memory management unit (MMU) and exception handling function. MMU checks whether there is an access between different memory segments (user, supervisor, and kernel) by executing address conversion.
Page 59: R 4120A Registers
CHAPTER 2 V 4120A 2.1.2 V 4120A registers The V 4120A has the following registers. general-purpose register (GPR): 64 bits × 32 In addition, the processor provides the following special registers: 64-bit Program Counter (PC) 64-bit HI register, containing the integer multiply and divide upper doubleword result 64-bit LO register, containing the integer multiply and divide lower doubleword result Two of the general-purpose registers have assigned the following functions: r0 is hardwired to a value of zero, and can be used as the target register for any instruction whose result is to...
Page 60: R 4120A Instruction Set Overview
CHAPTER 2 V 4120A 2.1.3 V 4120A instruction set overview For CPU instructions, there are only one type of instructions – 32-bit length instruction (MIPS III). 2.1.3.1 MIPS III instruction All the CPU instructions are 32-bit length when executing MIPS III instructions, and they are classified into three instruction formats as shown in Figure 2-3: immediate (I-type), jump (J-type), and register (R-type).
Page 61: Data Formats And Addressing
CHAPTER 2 V 4120A 2.1.4 Data formats and addressing The V 4120A uses following four data formats: Doubleword (64 bits) Word (32 bits) Halfword (16 bits) Byte (8 bits) For the µ PD98502, byte ordering within all of the larger data formats - halfword, word, doubleword - can be configured in either big-endian or little-endian order.
Page 62: Misaligned Word Accessing (Little-Endian)
CHAPTER 2 V 4120A The following special instructions to load and store data that are not aligned on 4-byte (word) or 8-byte (doubleword) boundaries: These instructions are used in pairs to provide an access to misaligned data. Accessing misaligned data incurs one additional instruction cycle over that required for accessing aligned data.
Page 63: Coprocessors (Cp0)
CHAPTER 2 V 4120A 2.1.5 Coprocessors (CP0) MIPS ISA defines 4 types of coprocessors (CP0 to CP3). • CP0 translates virtual addresses to physical addresses, switches the operating mode (kernel, supervisor, or user mode), and manages exceptions. It also controls the cache subsystem to analyze a cause and to return from the error state.
Page 64: Floating-Point Unit (Fpu)
CHAPTER 2 V 4120A Table 2-1. System Control Coprocessor (CP0) Register Definitions Register Register Name Description Number Index Programmable pointer to TLB array Random Pseudo-random pointer to TLB array (read only) EntryLo0 Low half of TLB entry for even VPN EntryLo1 Low half of TLB entry for odd VPN Context...
Page 65: Cpu Core Memory Management System (Mmu)
CHAPTER 2 V 4120A 2.1.7 CPU core memory management system (MMU) The V 4120A has a 32-bit physical addressing range of 4 Gbytes. However, since it is rare for systems to implement a physical memory space as large as that memory space, the CPU provides a logical expansion of memory space by translating addresses composed in the large virtual address space into available physical memory addresses.
Page 66: Instruction Pipeline
CHAPTER 2 V 4120A 2.1.11 Instruction pipeline The V 4120A has a 6-stage instruction pipeline. Under normal circumstances, one instruction is issued each cycle. A detailed description of pipeline is provided in Section 2.3 Pipeline. 2.2 MIPS III Instruction Set Summary This section is an overview of the MIPS III ISA central processing unit (CPU) instruction set;...
Page 67: Instruction Classes
CHAPTER 2 V 4120A 2.2.2 Instruction classes The CPU instructions are classified into five classes. 2.2.2.1 Load and store instructions Load and store are immediate (I-type) instructions that move data between memory and general registers. The only addressing mode that load and store instructions directly support is base register plus 16-bit signed immediate offset.
Page 68: Byte Specification Related To Load And Store Instructions
CHAPTER 2 V 4120A Table 2-3. Byte Specification Related to Load and Store Instructions Access Type Low-Order Accessed Byte (Value) Address Bit Little Endian Doubleword (7) 7-byte (6) 6-byte (5) 5-byte (4) Word (3) Triple byte (2) Halfword (1) Byte (0) Preliminary User’s Manual S15543EJ1V0UM...
Page 69: Load/Store Instruction
CHAPTER 2 V 4120A Table 2-4. Load/Store Instruction offset Instruction Format and Description base Load Byte LB rt, offset (base) The offset is sign extended and then added to the contents of the register base to form the virtual address. The bytes of the memory location specified by the address are sign extended and loaded into register rt.
Page 70: Load/Store Instruction (Extended Isa)
CHAPTER 2 V 4120A Table 2-5. Load/Store Instruction (Extended ISA) base offset Instruction Format and Description Store Word Left SWL rt, offset (base) The offset is sign extended and then added to the contents of the register base to form the virtual address.
Page 71: Alu Immediate Instruction
CHAPTER 2 V 4120A 2.2.2.2 Computational instructions Computational instructions perform arithmetic, logical, and shift operations on values in registers. Computational instructions can be either in register (R-type) format, in which both operands are registers, or in immediate (I-type) format, in which one operand is a 16-bit immediate. Computational instructions are classified as: (1) ALU immediate instructions (2) Three-operand type instructions...
Page 72: Alu Immediate Instruction (Extended Isa)
CHAPTER 2 V 4120A Table 2-7. ALU Immediate Instruction (Extended ISA) immediate Instruction Format and Description Doubleword Add DADDI rt, rs, immediate Immediate The 16-bit immediate is sign extended to 64 bits and then added to the contents of register rs to form a 64-bit result.
Page 73: Three-Operand Type Instruction (Extended Isa)
CHAPTER 2 V 4120A Table 2-9. Three-Operand Type Instruction (Extended ISA) funct Instruction Format and Description Doubleword Add DADD rd, rt, rs The contents of register rs are added to that of register rt. The 64-bit result is stored into register rd. An exception occurs on the generation of integer overflow.
Page 74: Shift Instruction (Extended Isa)
CHAPTER 2 V 4120A Table 2-11. Shift Instruction (Extended ISA) funct Instruction Format and Description Doubleword Shift Left DSLL rd, rt, sa Logical The contents of register rt are shifted left by sa bits and zeros are inserted into the emptied lower bits. The 64-bit result is stored into register rd.
Page 75: Multiply/Divide Instructions
CHAPTER 2 V 4120A Table 2-12. Multiply/Divide Instructions funct Instruction Format and Description Multiply MULT rs, rt The contents of registers rt and rs are multiplied, treating both operands as 32-bit signed integers. The 64-bit result is stored into special registers HI and LO. In the 64-bit mode, the operand must be sign extended.
Page 76: Multiply/Divide Instructions (Extended Isa)
CHAPTER 2 V 4120A Table 2-13. Multiply/Divide Instructions (Extended ISA) funct Instruction Format and Description Doubleword Multiply DMULT rs, rt The contents of registers rt and rs are multiplied, treating both operands as signed integers. The 128-bit result is stored into special registers HI and LO. Doubleword Multiply DMULTU rs, rt Unsigned...
Page 77: Number Of Stall Cycles In Multiply And Divide Instructions
CHAPTER 2 V 4120A Table 2-14. Number of Stall Cycles in Multiply and Divide Instructions Instruction Number of Instruction Cycles MULT MULTU DIVU DMULT DMULTU DDIV DDIVU MACC DMACC 2.2.2.3 Jump and branch instructions Jump and branch instructions change the control flow of a program. All jump and branch instructions occur with a delay of one instruction: that is, the instruction immediately following the jump or branch instruction (this is known as the instruction in the delay slot) always executes while the target instruction is being fetched from memory.
Page 78: Jump Instruction
CHAPTER 2 V 4120A Table 2-16. Jump Instruction target Instruction Format and Description Jump JAL target The contents of 26-bit target address is shifted left by two bits and combined with the high-order four bits of the PC. The program jumps to this calculated address with a delay of one instruction. Jump And Link J target The contents of 26-bit target address is shifted left by two bits and combined with the high-order four...
Page 79: Branch Instructions
CHAPTER 2 V 4120A There are special symbols used in the instruction formats of Tables 2-17 through 2-21. REGIMM : Opcode : Sub-operation code : Sub-operation identifier : BC sub-operation code : Branch condition identifier : Operation code Table 2-17. Branch Instructions offset Instruction Format and Description...
Page 80: Branch Instructions (Extended Isa)
CHAPTER 2 V 4120A Table 2-18. Branch Instructions (Extended ISA) offset Instruction Format and Description Branch On Equal Likely BEQL rs, rt, offset If the contents of register rs are equal to that of register rt, the program branches to the target address. If the branch condition is not met, the instruction in the delay slot is discarded.
Page 81: Special Instructions
CHAPTER 2 V 4120A 2.2.2.4 Special instructions Special instructions generate software exceptions. Their formats are R-type (Syscall, Break). The Trap instruction is available only for the V 4000 Series. All the other instructions are available for all V Series. Table 2-19. Special Instructions Instruction Format and Description SPECIAL...
Page 82: Special Instructions (Extended Isa) (2/2)
CHAPTER 2 V 4120A Table 2-20. Special Instructions (Extended ISA) (2/2) Instruction Format and Description immediate REGIMM Trap If Greater Than Or TGEI rs, immediate Equal Immediate The contents of register rs are compared with 16-bit sign-extended immediate data, treating both operands as signed integers.
Page 83: System Control Coprocessor (Cp0) Instructions (2/2)
CHAPTER 2 V 4120A Table 2-21. System Control Coprocessor (CP0) Instructions (2/2) funct Instruction Format and Description COP0 Read Indexed TLB TLBR Entry The TLB entry indexed by the index register is loaded into the entryHi, entryLo0, entryLo1, or page mask register.
Page 84: Pipeline
CHAPTER 2 V 4120A 2.3 Pipeline This section describes the basic operation of the V 4120A Core pipeline, which includes descriptions of the delay slots (instructions that follow a branch or load instruction in the pipeline), interrupts to the pipeline flow caused by interlocks and exceptions, and CP0 hazards.
Page 85: Instruction Execution In The Pipeline
CHAPTER 2 V 4120A Figure 2-10. Instruction Execution in the Pipeline (Five stages) PCycle IF2 RF1 RF2 EX1 EX2 DC1 DC2 WB1 WB2 IF2 RF1 RF2 EX1 EX2 DC1 DC2 WB1 WB2 IF2 RF1 RF2 EX1 EX2 DC1 DC2 WB1 WB2 IF2 RF1 RF2 EX1 EX2 DC1 DC2 WB1 WB2 IF2 RF1 RF2 EX1 EX2 DC1 DC2 WB1 WB2 Current CPU cycle...
Page 86: Operation In Each Stage Of Pipeline (Mips Iii)
CHAPTER 2 V 4120A Table 2-22. Operation in Each Stage of Pipeline (MIPS III) Cycle Phase Mnemonic Description Φ 1 Instruction cache address decode ITLB Instruction address translation Φ 2 Instruction cache array access Instruction tag check Φ 1 IDEC Instruction decode Φ...
Page 87: Branch Delay
CHAPTER 2 V 4120A 2.3.2 Branch delay During a V 4120A's pipeline operation, a one-cycle branch delay occurs when: • Target address is calculated by a Jump instruction • Branch condition of branch instruction is met and then logical operation starts for branch-destination comparison The instruction location following the Jump/Branch instruction is called a branch delay slot.
Page 88: Pipeline Operation
CHAPTER 2 V 4120A 2.3.4 Pipeline operation The operation of the pipeline is illustrated by the following examples that describe how typical instructions are executed. The instructions described are six: ADD, JALR, BEQ, TLT, LW, and SW. Each instruction is taken through the pipeline and the operations that occur in each relevant stage are described.
Page 89: Jalr Instruction Pipeline Activities (In Mips Iii Instruction Mode)
CHAPTER 2 V 4120A 2.3.4.2 Jump and link register instruction (JALR rd, rs) IF stage Same as the IF stage for the ADD instruction. IT stage Same as the IT stage for the ADD instruction. A register specified in the rs field is read from the file during Φ 2 at the RF stage, and the value RF stage read from the rs register is input to the virtual PC latch synchronously.
Page 90: Beq Instruction Pipeline Activities (In Mips Iii Instruction Mode)
CHAPTER 2 V 4120A 2.3.4.3 Branch on equal instruction (BEQ rs, rt, offset) IF stage Same as the IF stage for the ADD instruction. IT stage Same as the IT stage for the ADD instruction. During Φ 2, the register file is addressed with the rs and rt fields. A check is performed to RF stage determine if each corresponding bit position of these two operands has equal values.
Page 91: Tlt Instruction Pipeline Activities
CHAPTER 2 V 4120A 2.3.4.4 Trap if less than instruction (TLT rs, rt) IF stage Same as the IF stage for the ADD instruction. RF stage Same as the RF stage for the ADD instruction. EX stage ALU controls are set to do an A - B operation. The operands flow into the ALU inputs, and the ALU operation is started.
Page 92: Lw Instruction Pipeline Activities (In Mips Iii Instruction Mode)
CHAPTER 2 V 4120A 2.3.4.5 Load word instruction (LW rt, offset (base)) IF stage Same as the IF stage for the ADD instruction. IT stage Same as the IT stage for the ADD instruction. RF stage Same as the RF stage for the ADD instruction. Note that the base field is in the same position as the rs field.
Page 93: Sw Instruction Pipeline Activities (In Mips Iii Instruction Mode)
CHAPTER 2 V 4120A 2.3.4.6 Store word instruction (SW rt, offset (base)) IF stage Same as the IF stage for the ADD instruction. IT stage Same as the IT stage for the ADD instruction. RF stage Same as the RF stage for the LW instruction. EX stage Refer to the LW instruction for a calculation of the effective address.
Page 94: Interlock And Exception Handling
CHAPTER 2 V 4120A 2.3.5 Interlock and exception handling Smooth pipeline flow is interrupted when cache misses or exceptions occur, or when data dependencies are detected. Interruptions handled using hardware, such as cache misses, are referred to as interlocks, while those that are handled using software are called exceptions.
Page 95: Pipeline Interlock
CHAPTER 2 V 4120A Table 2-24. Pipeline Interlock Interlock Description Instruction TLB Miss Instruction Cache Miss Load Data Interlock MD Busy Interlock Store-Load Interlock Coprocessor 0 Interlock Data TLB Miss Data Cache Miss Data Cache Busy Table 2-25. Description of Pipeline Exception Exception Description IAErr...
Page 96: Exception Detection
CHAPTER 2 V 4120A 2.3.5.1 Exception conditions When an exception condition occurs, the relevant instruction and all those that follow it in the pipeline are cancelled. Accordingly, any stall conditions and any later exception conditions that may have referenced this instruction are inhibited;...
Page 97: Data Cache Miss Stall
CHAPTER 2 V 4120A 2.3.5.2 Stall conditions Stalls are used to stop the pipeline for conditions detected after the RF stage. When a stall occurs, the processor will resolve the condition and then the pipeline will continue. Figure 2-21 shows a data cache miss stall, and Figure 2- 22 shows a CACHE instruction stall.
Page 98: Load Data Interlock
CHAPTER 2 V 4120A 2.3.5.3 Slip conditions During Φ 2 of the RF stage and Φ1 of the EX stage, internal logic will determine whether it is possible to start the current instruction in this cycle. If all of the source operands are available (either from the register file or via the internal bypass logic) and all the hardware resources necessary to complete the instruction will be available whenever required, then the instruction “run”;...
Page 99: Md Busy Interlock
CHAPTER 2 V 4120A Figure 2-24. MD Busy Interlock Bypass MFLO/MFHI Detect MD busy interlock Get target data MD Busy Interlock is detected in the RF stage as shown in Figure 2-24 and also the pipeline slips in the stage. MD Busy Interlock occurs when HI/LO register is required by MFHI/MFLO instruction before finishing Mult/Div execution.
Page 100: Program Compatibility
CHAPTER 2 V 4120A 2.3.6 Program compatibility The V 4120A core is designed taking into consideration program compatibility with other V -Series processors. However, because the V 4120A differs from other processors in its architecture, it may not be able to run some programs that run on other processors.
Page 101: Memory Management System
CHAPTER 2 V 4120A 2.4 Memory Management System The V 4120A Core provides a memory management unit (MMU) which uses a translation lookaside buffer (TLB) to translate virtual addresses into physical addresses. This chapter describes the virtual and physical address spaces, the virtual-to-physical address translation, the operation of the TLB in making these translations, and the CP0 registers that provide the software interface to the TLB.
Page 102: Virtual Address Space
CHAPTER 2 V 4120A 2.4.2 Virtual address space This section describes the virtual/physical address space and the manner in which virtual addresses are converted or “translated” into physical addresses in the TLB. The V 4120A virtual address can be either 32 or 64 bits wide, depending on whether the processor is operating in 32-bit or 64-bit mode.
Page 103 CHAPTER 2 V 4120A 2.4.2.1 Virtual-to-physical address translation Converting a virtual address to a physical address begins by comparing the virtual address from the processor with the virtual addresses in the TLB; there is a match when the virtual page number (VPN) of the address is the same as the VPN field of the entry, and either: the Global (G) bit of the TLB entry is set to 1 the ASID field of the virtual address is the same as the ASID field of the TLB entry.
Page 104: Bit Mode Virtual Address Translation
CHAPTER 2 V 4120A 2.4.2.2 32-bit mode address translation Figure 2-26 shows the virtual-to-physical-address translation of a 32-bit mode address. The pages can have five different sizes between 1 Kbyte (10 bits) and 256 Kbytes (18 bits), each being 4 times as large as the preceding one in ascending order, that is 1 K, 4 K, 16 K, 64 K, and 256 K.
Page 105: Bit Mode Virtual Address Translation
CHAPTER 2 V 4120A 2.4.2.3 64-bit mode address translation Figure 2-27 shows the virtual-to-physical-address translation of a 64-bit mode address. This figure illustrates the two possible page size; a 1-Kbyte page (10 bits) and a 256-Kbyte page (18 bits). Shown at the top of Figure 2-27 is the virtual address space in which the page size is 1 Kbyte and the offset is 10 bits.
Page 106: User Mode Address Space
CHAPTER 2 V 4120A 2.4.2.4 Operating modes The processor has three operating modes that function in both 32- and 64-bit operations: User mode Supervisor mode Kernel mode User and Kernel modes are common to all V -Series processors. Generally, Kernel mode is used to execute the operating system, while User mode is used to run application programs.
Page 107: Comparison Of Useg And Xuseg
CHAPTER 2 V 4120A The User segment starts at address 0 and the current active user process resides in either useg (in 32-bit mode) or xuseg (in 64-bit mode). The TLB identically maps all references to useg/xuseg from all modes, and controls cache accessibility.
Page 108: Supervisor Mode Address Space
CHAPTER 2 V 4120A 2.4.2.6 Supervisor-mode virtual addressing Supervisor mode shown in Figure 2-29 is designed for layered operating systems in which a true kernel runs in Kernel mode, and the rest of the operating system runs in Supervisor mode. The processor operates in Supervisor mode when the Status register contains the following bit-values: KSU = 01 EXL = 0...
Page 109: Bit And 64-Bit Supervisor Mode Segments
CHAPTER 2 V 4120A Table 2-28. 32-bit and 64-bit Supervisor Mode Segments Address Bit Status Register Bit Value Segment Address Range Size Value Name 32-bit suseg 0000_0000H 2 Gbytes A31 = 0 bytes) 7FFF_FFFFH 32-bit sseg C000_0000H A(31:29) = Mbytes DFFF_FFFFH bytes) 64-bit...
Page 110 CHAPTER 2 V 4120A 2.4.2.7 Kernel-mode virtual addressing If the Status register satisfies any of the following conditions, the processor runs in Kernel mode. KSU = 00 EXL = 1 ERL = 1 The addressing width in Kernel mode varies according to the state of the KX bit of the Status register, as follows: When KX = 0: 32-bit kernel space is selected.
Page 111: Kernel Mode Address Space
CHAPTER 2 V 4120A Figure 2-30. Kernel Mode Address Space Note 1 32-bit mode 64-bit mode FFFF_ FFFFH FFFF_ FFFF_ FFFF_ FFFFH 0.5 Gbytes with 0.5 Gbytes with ckseg TLB mapping kseg3 TLB mapping FFFF_ FFFF_ E000_ 0000H FFFF_ FFFF_ DFFF_ FFFFH E000_ 0000H 0.5 Gbytes with cksseg...
Page 112: Bit Kernel Mode Segments
CHAPTER 2 V 4120A Table 2-29. 32-bit Kernel Mode Segments Address Bit Status Register Bit Value Segment Virtual Physical Size Value Name Address Address A31 = 0 KSU = 00 kuseg 0000_0000H TLB map 2 Gbytes bytes) EXL = 1 7FFF_FFFFH A(31:29) = 100 kseg0...
Page 113: Bit Kernel Mode Segments
CHAPTER 2 V 4120A (5) kseg3 (32-bit kernel mode, kernel space 3) When KX = 0 in the Status register and the most-significant three bits of the virtual address space are 111, the kseg3 virtual address space is selected; it is the current 512-Mbyte (2 -byte) kernel virtual space.
Page 114: Cacheability And Xkphys Address Space
CHAPTER 2 V 4120A (7) xksseg (64-bit kernel mode, current supervisor space) When KX = 1 in the Status register and bits 63 and 62 of the virtual address space are 01, the xksseg address space is selected; it is the 1-Tbyte (2 bytes) current supervisor address space.
Page 115 CHAPTER 2 V 4120A (9) xkseg (64-bit kernel mode, physical spaces) When the KX = 1 in the Status register and bits 63 and 62 of the virtual address space are 11, the virtual address space is called xkseg and selected as either of the following: •...
Page 116: Physical Address Space
CHAPTER 2 V 4120A 2.4.3 Physical address space So V 4120A core uses a 32-bit address, that the processor physical address space encompasses 4 Gbytes. The 4120A uses this 4-Gbyte physical address space as shown in Figure 2-31. Figure 2-31. µ µ µ µ PD98502 Physical Address Space FFFF_FFFFH M irror of 0000_0000H - 1FFF_FFFF...
Page 117: System Control Coprocessor
CHAPTER 2 V 4120A 2.4.4 System control coprocessor The System Control Coprocessor (CP0) is implemented as an integral part of the CPU, and supports memory management, address translation, exception processing, and other privileged operations. The CP0 contains the registers and a 32-entry TLB shown in Figure 2-32. The sections that follow describe how the processor uses each of the memory management-related registers.
Page 118: Format Of A Tlb Entry
CHAPTER 2 V 4120A 2.4.4.1 Format of a TLB entry Figure 2-33 shows the TLB entry formats for both 32- and 64-bit modes. Each field of an entry has a corresponding field in the EntryHi, EntryLo0, EntryLo1, or PageMask registers. Figure 2-33.
Page 119: Cp0 Registers
CHAPTER 2 V 4120A 2.4.5 CP0 registers The CP0 registers explained below are accessed by the memory management system and software. parenthesized number that follows each register name is the register number. 2.4.5.1 Index register (0) The Index register is a 32-bit, read/write register containing five low-order bits to index an entry in the TLB. The most-significant bit of the register shows the success or failure of a TLB probe (TLBP) instruction.
Page 120: Entrylo0 And Entrylo1 Registers
CHAPTER 2 V 4120A 2.4.5.3 EntryLo0 (2) and EntryLo1 (3) registers The EntryLo register consists of two registers that have identical formats: EntryLo0, used for even virtual pages and EntryLo1, used for odd virtual pages. The EntryLo0 and EntryLo1 registers are both read-/write-accessible. They are used to access the on-chip TLB.
Page 121: Page Mask Register
CHAPTER 2 V 4120A Table 2-32. Cache Algorithm C Bit Value Cache Algorithm Cached Cached Uncached Cached Cached Cached Cached Cached 2.4.5.4 PageMask register (5) The PageMask register is a read/write register used for reading from or writing to the TLB; it holds a comparison mask that sets the page size for each TLB entry, as shown in Table 2-33.
Page 122: Positions Indicated By Wired Register
CHAPTER 2 V 4120A 2.4.5.5 Wired register (6) The Wired register is a read/write register that specifies the lower boundary of the random entry of the TLB as shown in Figure 2-38. Wired entries cannot be overwritten by a TLBWR instruction. They can, however, be overwritten by a TLBWI instruction.
Page 123: Entryhi Register
CHAPTER 2 V 4120A 2.4.5.6 EntryHi register (10) The EntryHi register is write-accessible. It is used to access the on-chip TLB. The EntryHi register holds the high- order bits of a TLB entry for TLB read and write operations. If a TLB Mismatch, TLB Invalid, or TLB Modified exception occurs, the EntryHi register holds the high-order bit of the TLB entry.
Page 124: Config Register Format
CHAPTER 2 V 4120A 2.4.5.8 Config register (16) The Config register specifies various configuration options selected on V 4120A processors. Some configuration options, as defined by the EC and BE fields, are set by the hardware during Cold Reset and are included in the Config register as read-only status bits for the software to access.
Page 125: Lladdr Register
CHAPTER 2 V 4120A 2.4.5.9 Load linked address (LLAddr) register (17) The read/write Load Linked Address (LLAddr) register is not used with the V 4120A processor except for diagnostic purpose, and serves no function during normal operation. LLAddr register is implemented just for compatibility between the V 4120A and V 4000/V 4400.
Page 126 CHAPTER 2 V 4120A 2.4.5.11 Virtual-to-physical address translation During virtual-to-physical address translation, the CPU compares the 8-bit ASID (when the Global bit, G, is not set to 1) of the virtual address to the ASID of the TLB entry to see if there is a match. One of the following comparisons are also made: Note 1 In 32-bit mode, the high-order bits...
Page 127: Tlb Address Translation
CHAPTER 2 V 4120A Figure 2-46. TLB Address Translation Virtual address (input) ASID User Address Address Supervisor mode? mode? Address Address error error Address Address error Exception Exception Exception Mapped match? address? Global ASID G = 1? match? Valid 32-bit V = 1? address? Dirty...
Page 128 CHAPTER 2 V 4120A 2.4.5.13 TLB instructions The instructions used for TLB control are described below. (1) Translation lookaside buffer probe (TLBP) The translation lookaside buffer probe (TLBP) instruction loads the Index register with a TLB number that matches the content of the EntryHi register. If there is no TLB number that matches the TLB entry, the highest-order bit of the Index register is set.
Page 129: Exception Processing
CHAPTER 2 V 4120A 2.5 Exception Processing This chapter describes V 4120A CPU exception processing, including an explanation of hardware that processes exceptions. 2.5.1 Exception processing operation The processor receives exceptions from a number of sources, including translation lookaside buffer (TLB) misses, arithmetic overflows, I/O interrupts, and system calls.
Page 130: Precision Of Exceptions
CHAPTER 2 V 4120A 2.5.2 Precision of exceptions 4120A CPU exceptions are logically precise; the instruction that causes an exception and all those that follow it are aborted and can be re-executed after servicing the exception. When succeeding instructions are discarded, exceptions associated with those instructions are also discarded.
Page 131: Context Register Format
CHAPTER 2 V 4120A 2.5.3.1 Context register (4) The Context register is a read/write register containing the pointer to an entry in the page table entry (PTE) array on the memory; this array is a table that stores virtual-to-physical address translations. When there is a TLB miss, the operating system loads the unsuccessfully translated entry from the PTE array to the TLB.
Page 132: Badvaddr Register Format
CHAPTER 2 V 4120A 2.5.3.2 BadVAddr register (8) The Bad Virtual Address (BadVAddr) register is a read-only register that saves the most recent virtual address that failed to have a valid translation, or that had an addressing error. Figure 2-48 shows the format of the BadVAddr register.
Page 133: Compare Register Format
CHAPTER 2 V 4120A 2.5.3.4 Compare register (11) The Compare register causes a timer interrupt; it maintains a stable value that does not change on its own. When the value of the Count register (see Section 2.5.3.3 Count register (9)) equals the value of the Compare register, the IP7 bit in the Cause register is set.
Page 134: Status Register Format
CHAPTER 2 V 4120A 2.5.3.5 Status register (12) The Status register is a read/write register that contains the operating mode, interrupt enabling, and the diagnostic states of the processor. Figure 2-51 shows the format of the Status register. Figure 2-51. Status Register Format 29 28 27 26 25 24 16 15 KX SX UX...
Page 135: Status Register Diagnostic Status Field
CHAPTER 2 V 4120A Figure 2-52. Status Register Diagnostic Status Field : Specifies the base address of a TLB Refill exception vector and common exception vector (0 → Normal, 1 → Bootstrap). : Occurs the TLB to be shut down (read-only) (0 → Not shut down, 1 → Shut down). This bit is used to avoid any problems that may occur when multiple TLB entries match the same virtual address.
Page 136: Cause Register Format
CHAPTER 2 V 4120A (7) Status after reset The contents of the Status register are undefined after Cold resets, except for the following bits in the diagnostic status field. • TS and SR are cleared to 0. • ERL and BEV are set to 1. •...
Page 137: Cause Register Exception Code Field
CHAPTER 2 V 4120A Table 2-35. Cause Register Exception Code Field Exception Code Mnemonic Description Interrupt exception TLB Modified exception TLBL TLB Refill exception (load or fetch) TLBS TLB Refill exception (store) AdEL Address Error exception (load or fetch) AdES Address Error exception (store) Bus Error exception (instruction fetch) Bus Error exception (data load or store)
Page 138: Epc Register Format
CHAPTER 2 V 4120A 2.5.3.7 Exception program counter (EPC) register (14) The Exception Program Counter (EPC) is a read/write register that contains the address at which processing resumes after an exception has been serviced. Because the µ PD98502 does not support the MIPS16 instruction mode, the EPC register contains either: •...
Page 139: Watchlo Register Format
CHAPTER 2 V 4120A 2.5.3.8 WatchLo (18) and WatchHi (19) registers The V 4120A processor provides a debugging feature to detect references to a selected physical address; load and store instructions to the location specified by the WatchLo and WatchHi registers cause a Watch exception. Figures 2-55 and 2-56 show the format of the WatchLo and WatchHi registers.
Page 140: Xcontext Register Format
CHAPTER 2 V 4120A 2.5.3.9 XContext register (20) The read/write XContext register contains a pointer to an entry in the page table entry (PTE) array, an operating system data structure that stores virtual-to-physical address translations. If a TLB miss occurs, the operating system loads the untranslated data from the PTE into the TLB to handle the software error.
Page 141: Cache Error Register Format
CHAPTER 2 V 4120A 2.5.3.11 Cache error register (27) The Cache Error register is a readable/writeable register. This register is defined to maintain software-compatibility with the V 4100, and is not used in hardware because the V 4120A CPU has no parity. Figure 2-59 shows the format of the Cache Error register.
Page 142: Details Of Exceptions
CHAPTER 2 V 4120A 2.5.4 Details of exceptions This section describes causes, processes, and services of the V 4120A's exceptions. 2.5.4.1 Exception types This section gives sample exception handler operations for the following exception types: Cold Reset Soft Reset Remaining processor exceptions When the EXL and ERL bits in the Status register are 0, either User, Supervisor, or Kernel operating mode is specified by the KSU bits in the Status register.
Page 143: Bit Mode Exception Vector Base Addresses
CHAPTER 2 V 4120A Table 2-37. 32-Bit Mode Exception Vector Base Addresses Vector Base Address (Virtual) Vector Offset Cold Reset BFC0_0000H 0000H Soft Reset (BEV bit is automatically set to 1) TLB Refill (EXL = 0) 8000_0000H (BEV = 0) 0000H BFC0_0200H (BEV = 1) XTLB Refill (EXL = 0)
Page 144: Exception Priority Order
CHAPTER 2 V 4120A 2.5.4.3 Priority of exceptions While more than one exception can occur for a single instruction, only the exception with the highest priority is reported. Table 2-38 lists the priorities. Table 2-38. Exception Priority Order High Cold Reset ↑...
Page 145 CHAPTER 2 V 4120A 2.5.4.4 Cold reset exception (1) Cause The Cold Reset exception occurs when the ColdReset_B signal (internal) is asserted and then deasserted. This exception is not maskable. The Reset_B signal (internal) must be asserted along with the ColdReset_B signal (for details, see Section 2.6 Initialization Interface).
Page 146 CHAPTER 2 V 4120A 2.5.4.5 Soft reset exception (1) Cause A Soft Reset (sometimes called Warm Reset) occurs when the ColdReset_B signal (internal) remains deasserted while the Reset_B signal (internal) goes from assertion to deassertion (for details, see Section 2.6 Initialization Interface).
Page 147 CHAPTER 2 V 4120A 2.5.4.6 NMI exception (1) Cause The Nonmaskable Interrupt (NMI) exception occurs when the NMI signal (internal) becomes active. This interrupt is not maskable; it occurs regardless of the settings of the EXL, ERL, and IE bits in the Status register (for details, see Section 2.8 CPU Core Interrupts).
Page 148 CHAPTER 2 V 4120A 2.5.4.7 Address error exception (1) Cause The Address Error exception occurs when an attempt is made to execute one of the following. This exception is not maskable. • Execution of the LW, LWU, SW, or CACHE instruction for word data that is not located on a word boundary •...
Page 149 CHAPTER 2 V 4120A 2.5.4.8 TLB exceptions Three types of TLB exceptions can occur: • TLB Refill exception occurs when there is no TLB entry that matches a referenced address. • A TLB Invalid exception occurs when a TLB entry that matches a referenced virtual address is marked as being invalid (with the V bit set to 0).
Page 150 CHAPTER 2 V 4120A (2) TLB invalid exception (a) Cause The TLB Invalid exception occurs when the TLB entry that matches with the virtual address to be referenced is invalid (the V bit is set to 0). This exception is not maskable. (b) Processing The common exception vector is used for this exception.
Page 151 CHAPTER 2 V 4120A (3) TLB modified exception (a) Cause The TLB Modified exception occurs when the TLB entry that matches with the virtual address referenced by the store instruction is valid (V bit is 1) but is not writeable (D bit is 0). This exception is not maskable. (b) Processing The common exception vector is used for this exception, and the Mod code in the ExcCode field of the Cause register is set.
Page 152 CHAPTER 2 V 4120A 2.5.4.9 Bus error exception (1) Cause A Bus Error exception is raised by board-level circuitry for events such as bus time-out, local bus parity errors, and invalid physical memory addresses or access types. This exception is not maskable. A Bus Error exception occurs only when a cache miss refill, uncached reference, or unbuffered write occurs simultaneously.
Page 153 CHAPTER 2 V 4120A 2.5.4.10 System call exception (1) Cause A System Call exception occurs during an attempt to execute the SYSCALL instruction. This exception is not maskable. (2) Processing The common exception vector is used for this exception, and the Sys code in the ExcCode field of the Cause register is set.
Page 154 CHAPTER 2 V 4120A 2.5.4.12 Coprocessor unusable exception (1) Cause The Coprocessor Unusable exception occurs when an attempt is made to execute a coprocessor instruction for either: a corresponding coprocessor unit that has not been marked usable (Status register bit, CU0 = 0), or CP0 instructions, when the unit has not been marked usable (Status register bit, CU0 = 0) and the process executes in User or Supervisor mode.
Page 155 CHAPTER 2 V 4120A 2.5.4.13 Reserved instruction exception (1) Cause The Reserved Instruction exception occurs when an attempt is made to execute one of the following instructions: • Instruction with an undefined major opcode (bits 31 to 26) • SPECIAL instruction with an undefined minor opcode (bits 5 to 0) •...
Page 156 CHAPTER 2 V 4120A 2.5.4.14 Trap exception (1) Cause The Trap exception occurs when a TGE, TGEU, TLT, TLTU, TEQ, TNE, TGEI, TGEUI, TLTI, TLTUI, TEQI, or TNEI instruction results in a TRUE condition. This exception is not maskable. (2) Processing The common exception vector is used for this exception, and the Tr code in the ExcCode field of the Cause register is set.
Page 157 CHAPTER 2 V 4120A 2.5.4.16 Watch exception (1) Cause A Watch exception occurs when a load or store instruction references the physical address specified by the WatchLo/WatchHi registers. The WatchLo/WatchHi registers specify whether a load or store or both could have initiated this exception.
Page 158: Exception Processing And Servicing Flowcharts
CHAPTER 2 V 4120A 2.5.4.17 Interrupt exception (1) Cause Note The Interrupt exception occurs when one of the eight interrupt conditions is asserted. In the V 4120A CPU, interrupt requests from internal peripheral units first enter the ICU and are then notified to the CPU core via one of four interrupt sources (Int(3:0)) or NMI.
Page 159: Common Exception Handling
CHAPTER 2 V 4120A Figure 2-61. Common Exception Handling (1/2) (a) Handling Exceptions other than Cold Reset, Soft Reset, NMI, and TLB/XTLB Refill (Hardware) Start Entry Hi ← VPN2, ASID • EntryHi and X/Context registers are set only X/Context ← VPN2 when a TLB Refill, TLB Invalid, or TLB Set Cause register (ExcCode, CE) Modified exception occurs.
Page 160 CHAPTER 2 V 4120A Figure 2-61. Common Exception Handling (2/2) (b) Servicing Common Exceptions (Software) • The occurrence of TLB Refill, TLB Invalid, and TLB Modified Execute MFC0 instruction exceptions is disabled by using an unmapped space. X/Context register • The occurrence of the Watch and Interrupt exceptions is EPC register disabled by setting EXL = 1.
Page 161: Tlb/Xtlb Refill Exception Handling
CHAPTER 2 V 4120A Figure 2-62. TLB/XTLB Refill Exception Handling (1/2) (a) Handling TLB/XTLB Refill Exceptions (Hardware) Start EntryHi←VPN2, ASID X/Context←VPN2 Set Cause register (ExcCode, CE) Check for multiple exceptions EXL = 1? (SR1) M16 = 1? Instruction (config20) in delay slot? BD bit←0 BD bit←1 EPC←PC...
Page 162 CHAPTER 2 V 4120A Figure 2-62. TLB/XTLB Refill Exception Handling (2/2) (b) Servicing TLB/XTLB Refill Exceptions (Software) • The occurrence of TLB Refill, TLB Invalid, and TLB Modified exceptions is disabled by using an unmapped space. Execute MFC0 instruction • The occurrence of the Watch and Interrupt exceptions is X/Context register disabled by setting EXL= 1.
Page 163: Cold Reset Exception Handling
CHAPTER 2 V 4120A Figure 2-63. Cold Reset Exception Handling (Hardware) Cold Reset Exception ERL=1? M16=1? (config20) Instruction in delay slot? BD bit←1 BD bit←0 Instruction ErrorEPC←PC−4 ErrorEPC← PC in branch delay ErrorEPC←EIM ErrorEPC←EIM slot? BD bit ← 1 BD bit ← 0 ErrorEPC ←...
Page 164: Soft Reset And Nmi Exception Handling
CHAPTER 2 V 4120A Figure 2-64. Soft Reset and NMI Exception Handling (Hardware) Soft Reset or NMI exception ERL=1? M16=1? (config20) Instruction in delay slot? BD bit←1 BD bit←0 Instruction ErrorEPC←PC−4 ErrorEPC←PC in branch delay ErrorEPC←EIM ErrorEPC←EIM slot? BD bit←1 BD bit←0 ErrorEPC←PC−4 ErrorEPC←PC...
Page 165: Initialization Interface
CHAPTER 2 V 4120A 2.6 Initialization Interface This section describes the reset sequence of the V 4120A Core. For details about factors of reset or reset of the whole V 4120A Core. 2.6.1 Cold reset In the V 4120A Core, a cold reset sequence is executed in the CPU core in the following cases: •...
Page 166 CHAPTER 2 V 4120A 2.6.3.1 Power modes The V 4120A supports four power modes: Fullspeed mode, Standby mode, Suspend mode, and Hibernate mode. (1) Fullspeed mode This is the normal operation mode. The V 4120A’s default status sets operation under Fullspeed mode. After the processor is reset, the V 4120A returns to Fullspeed mode.
Page 167 CHAPTER 2 V 4120A 2.6.3.2 Privilege mode The V 4120A supports three system modes: kernel expanded addressing mode, supervisor expanded addressing mode, and user expanded addressing mode. These three modes are described below. (1) Kernel expanded addressing mode When the Status register’s KX bit has been set, an expanded TLB miss exception vector is used when a TLB miss occurs for the kernel address.
Page 168: Cache Memory
CHAPTER 2 V 4120A 2.7 Cache Memory This section describes in detail the cache memory: its place in the V 4120A Core memory organization, and individual organization of the caches. 2.7.1 Memory organization Figure 2-65 shows the V 4120A Core system memory hierarchy. In the logical memory hierarchy, the caches lie between the CPU and main memory.
Page 169: Cache Organization
CHAPTER 2 V 4120A 2.7.2 Cache organization This section describes the organization of the on-chip data and instruction caches. Figure 2-66 provides a block diagram of the V 4120A Core cache and memory model. Figure 2-66. Cache Support 4120A CPU core Cache controller Main memory I-cache...
Page 170: Instruction Cache Line Format
CHAPTER 2 V 4120A Figure 2-67. Instruction Cache Line Format PTag Data Data Data Data PTag : Physical tag (bits 31 to 10 of physical address) : Valid bit Data : Cache data 2.7.2.2 Organization of the data cache (D-cache) Each line of D-cache data has an associated 25-bit tag that contains a 22-bit physical address, a Valid bit, a Dirty bit, and a Write-back bit.
Page 171: Cache Operations
CHAPTER 2 V 4120A 2.7.2.3 Accessing the caches Figure 2-69 shows the virtual address (VA) index into the caches. The number of virtual address bits used to index the instruction and data caches depends on the cache size. (1) Data cache addressing Using VA (12:4).
Page 172: Cache States
CHAPTER 2 V 4120A 2.7.3.1 Cache write policy The V 4120A Core manages its data cache by using a write-back policy; that is, it stores write data into the cache, Note instead of writing it directly to memory . Some time later this data is independently written into memory. In the 4120A implementation, a modified cache line is not written back to memory until the cache line is to be replaced either in the course of satisfying a cache miss, or during the execution of a write-back CACHE instruction.
Page 173: Cache State Transition Diagrams
CHAPTER 2 V 4120A 2.7.5 Cache state transition diagrams The following section describes the cache state diagrams for the data and instruction cache lines. These state diagrams do not cover the initial state of the system, since the initial state is system-dependent. 2.7.5.1 Data cache state transition The following diagram illustrates the data cache state transition sequence.
Page 174: Cache Data Integrity
CHAPTER 2 V 4120A 2.7.6 Cache data integrity Figures 2-72 to 2-86 shows checking operations for various cache accesses. Figure 2-72. Data Check Flow on Instruction Fetch Start Tag Check Miss Refill (See Figure 2-85) Data Fetch Figure 2-73. Data Check Flow on Load Operations Start Tag Check Miss or...
Page 175: Data Check Flow On Store Operations
CHAPTER 2 V 4120A Figure 2-74. Data Check Flow on Store Operations Start Tag Check Miss V = 0 (invalid) W = 0 (clean) V bit, W bit V = 1 ( valid) and W = 1 (dirty) Refill (see Figure 2-85) Write-back and Refill (see...
Page 176: Data Check Flow On Index_Writeback_Invalidate Operations
CHAPTER 2 V 4120A Figure 2-76. Data Check Flow on Index_Writeback_Invalidate Operations Start = 0 ( Invalid ) V bit = 1 ( Valid ) = 0 ( Clean ) W bit = 1 (dirty) Write-back (see Figure 2-84) Valid bit and W bit Clear Figure 2-77.
Page 177: Data Check Flow On Index_Store_Tag Operations
CHAPTER 2 V 4120A Figure 2-78. Data Check Flow on Index_Store_Tag Operations Start Tag Write from TagLo Figure 2-79. Data Check Flow on Create_Dirty Operations Start Miss or Invalid Tag Check = 0 (Clean) V bit, W bit = 1 ( dirty ) Write-back (see Figure 2-84) V bit and W bit set,...
Page 178: Data Check Flow On Hit_Invalidate Operations
CHAPTER 2 V 4120A Figure 2-80. Data Check Flow on Hit_Invalidate Operations Start Miss or Invalid Tag Check Valid bit Clear Figure 2-81. Data Check Flow on Hit_Writeback_Invalidate Operations Start Miss or Invalid Tag Check = 0 ( Clean ) W bit = 1 (dirty) Write-back...
Page 179: Data Check Flow On Fill Operations
CHAPTER 2 V 4120A Figure 2-82. Data Check Flow on Fill Operations Start Refill (see Figure 2-85) Figure 2-83. Data Check Flow on Hit_Writeback Operations Start Miss or Invalid Tag Check = 0 (Clean) W bit Data cache only = 1 (dirty) Write-back (see Figure 2-84) Data cache only...
Page 180: Writeback Flow
CHAPTER 2 V 4120A Figure 2-84. Writeback Flow Write-back to memory EOD ? Figure 2-85. Refill Flow Write data to Cache EOD ? Error Error bit Cache line Invalid Bus Error Exception Preliminary User’s Manual S15543EJ1V0UM...
Page 181: Manipulation Of The Caches By An External Agent
CHAPTER 2 V 4120A Figure 2-86. Writeback & Refill Flow Write-back to memory EOD ? Refill Start Error Error bit Write data Cache line to cache Invalid Bus Error Exception EOD ? Remark Write-back Procedure: On a store miss write-back, data tag is checked and data is transferred to the write buffer. If an error is detected in the data field, the write back is not terminated;...
Page 182: Cpu Core Interrupts
CHAPTER 2 V 4120A 2.8 CPU Core Interrupts Four types of interrupt are available on the CPU core. These are: one non-maskable interrupt, NMI five ordinary interrupts two software interrupts one timer interrupt For the interrupt request input to the CPU core. 2.8.1 Non-maskable interrupt (NMI) The non-maskable interrupt is acknowledged by asserting the NMI signal (internal), forcing the processor to branch to the Reset Exception vector.
Page 183: Asserting Interrupts
CHAPTER 2 V 4120A 2.8.5 Asserting interrupts 2.8.5.1 Detecting hardware interrupts Figure 2-88 shows how the hardware interrupts are readable through the Cause register. The timer interrupt signal, IP7, is directly readable as bit 15 of the Cause register. Bits 4 to 0 of the Interrupt register are bit-wise ORed with the current value of the Int4 to 0 signals and the result is directly readable as bits 14 to 10 of the Cause register.
Page 184: Masking Of Interrupt Request Signals
CHAPTER 2 V 4120A 2.8.5.2 Masking interrupt signals Figure 2-89 shows the masking of the CPU core interrupt signals. Cause register bits 15 to 8 (IP7 to IP0) are AND-ORed with Status register interrupt mask bits 15 to 8 (IM7 to IM0) to mask individual interrupts.
Page 185: Chapter 3 System Controller
This block is an internal system controller for the µ PD98502. System controller provides bridging function among the CPU system bus “SysAD”, NEC original high-speed on-chip bus “IBUS” and memory bus for SDRAM/PROM/flash. Features of system controller are as follows.
Page 186: Uart
CHAPTER 3 SYSTEM CONTROLLER • 66-MHz IBUS clock rate • Supports 266-MB/sec (32 bits @66 MHz) bursts on IBUS. • Support endian conversion between memory and IBUS slave I/F • Support endian conversion between SyaAD bus and IBUS master I/F 3.1.4 UART •...
Page 187: System Block Diagram
CHAPTER 3 SYSTEM CONTROLLER 3.1.9 System block diagram SysAD System Controller SysAD-IF SysAD-IF Prefetch Write Buffer Buffer Register TIMER Flash Write Flash-IF Memory PROM Buffer SDRAM- Arbiter SDRAM UART RS-232C MICRO Serial WIRE 64-word 64-word Read Write Buffer Buffer Read Buffer IBUS Slave-IF IBUS Master-IF...
Page 188: Data Flow Diagram
CHAPTER 3 SYSTEM CONTROLLER 3.1.10 Data flow diagram 4 1 2 0 A C o re to S D R A M IB U S to S D R A M S y sAD S y sAD M IF H IF M IF H IF S ys AD -IF...
Page 189: Registers
CHAPTER 3 SYSTEM CONTROLLER 3.2 Registers 3.2.1 Register map Following Table summarizes the controller’s register set. The base address for the set is 1000_0000H in the physical address space. Offset Address Register Name Access Description 1000_0000H S_GMR W/H/B General Mode Register 1000_0004H S_GSR W/H/B...
Page 190 CHAPTER 3 SYSTEM CONTROLLER Offset Address Register Name Access Description 1000_00D8H MACAR1 W/H/B MAC Address Register 1 1000_00DCH MACAR2 W/H/B MAC Address Register 2 1000_00E0H MACAR3 W/H/B MAC Address Register 3 1000_00E4H: Reserved for future use 1000_00FCH 1000_0100H RMMDR Boot ROM Mode Register 1000_0104H RMATR Boot ROM Access Timing Register...
Page 191: S_Gmr (General Mode Register)
CHAPTER 3 SYSTEM CONTROLLER 3.2.2 S_GMR (General Mode Register) The general mode register “S_GMR” is a read-write and 32-bit word-aligned register. After initializing, V 4120A sets the IAEN bit to enable the IBUS arbiter. S_GMR is initialized to 0 at reset and contains the following fields: Bits Field Default...
Page 192: S_Isr (Interrupt Status Register)
CHAPTER 3 SYSTEM CONTROLLER 3.2.4 S_ISR (Interrupt Status Register) The interrupt status register “S_ISR” is a read-clear and 32-bit word-aligned register. S_ISR indicates the interruption status from SysAD/IBUS interfaces, timer, UART and so on. If corresponding bit in S_IMR (Interrupt Mask Register) is set and the interrupt is not masked, system controller interrupts to V 4120A using interrupt signal.
Page 193: S_Imr (Interrupt Mask Register)
CHAPTER 3 SYSTEM CONTROLLER 3.2.5 S_IMR (Interrupt Mask Register) The interrupt mask register “S_IMR” is a read-write and 32-bit word-aligned register. S_IMR masks interruption for each corresponding incident. A mask bit, which locates in the same bit location to a corresponding bit in S_ISR, controls interruption triggered by the incident.
Page 194: S_Nsr (Nmi Status Register)
CHAPTER 3 SYSTEM CONTROLLER 3.2.6 S_NSR (NMI Status Register) The interrupt status register “S_NSR” is a read-clear and 32-bit word-aligned register. S_NSR indicates the non- maskable interruption “NMI” status from SysAD/IBUS interfaces, external NMI, memory interface and so on. If corresponding bit in S_NER (NMI Enable Register) is set and the NMI is enabled, system controller interrupts to 4120A using non-maskable interrupt signal.
Page 195: S_Ner (Nmi Enable Register)
CHAPTER 3 SYSTEM CONTROLLER 3.2.7 S_NER (NMI Enable Register) The NMI enable register “S_NER” is a read-write and 32-bit word-aligned register. S_NER enables NMI for each corresponding incident. A enable bit, which locates in the same bit location to a corresponding bit in S_NSR, controls interruption triggered by the incident.
Page 196: S_Ior (Io Port Register)
CHAPTER 3 SYSTEM CONTROLLER 3.2.9 S_IOR (IO Port Register) The IO port register “S_IOR” is a read-write and 32-bit word-aligned register. IO port register is used to indicate the status of software. Each bit of the following POM_OUT fields is connected to the external IO port (POM[7:0]) directly. S_IOR is initialized to 0 at reset and contains the following fields: Bits Field...
Page 197: S_Wrcr (Warm Reset Control Register)
CHAPTER 3 SYSTEM CONTROLLER 3.2.10 S_WRCR (Warm Reset Control Register) The warm reset control register “S_WRCR” is a write-only and 32-bit word-aligned register. S_WRCR generates warm-reset request to USB Controller, Ethernet Controller, ATM Cell Processor, UART, and PCI Controller independently. S_WRCR is initialized to 0 at reset and contains the following fields: Bits Field Default...
Page 198: S_Wrsr (Warm Reset Status Register)
CHAPTER 3 SYSTEM CONTROLLER 3.2.11 S_WRSR (Warm Reset Status Register) The warm reset status register “S_WRSR” is a read-only and 32-bit word-aligned register. S_WRSR indicates the response from USB Controller, Ethernet Controller, ATM Cell Processor, UART, and PCI Controller independently. S_WRSR is initialized to 0 at reset and contains the following fields: Bits Field...
Page 199: S_Pwcr (Power Control Register)
CHAPTER 3 SYSTEM CONTROLLER 3.2.12 S_PWCR (Power Control Register) The power control register “S_PWCR” is a read-write and 32-bit word-aligned register. S_PWCR requests to keep the idle state for USB Controller, Ethernet Controller, ATM Cell Processor, and PCI Controller by setting following IDRQ fields.
Page 200: S_Pwsr (Power Status Register)
CHAPTER 3 SYSTEM CONTROLLER 3.2.13 S_PWSR (Power Status Register) The power status register “S_PWSR” is a read-only and 32-bit word-aligned register. The IDLE field in S_PWSR indicates the status that it is ready to suspend. The WKUP filed in S_PWSR indicates the wakeup request. When a bit of IDLE fields gets 1, V 4120A can disable the system clock for the corresponding device by setting the STOP field in S_PWCR.
Page 201: Cpu Interface
CHAPTER 3 SYSTEM CONTROLLER 3.3 CPU Interface The system controller provides the direct interface for the V 4120A using the 32-bit SysAD bus operated at 100 MHz or 66 MHz. 3.3.1 Overview • Connects to the V 4120A CPU bus “SysAD bus” directly. •...
Page 202: Endian Configuration Table
CHAPTER 3 SYSTEM CONTROLLER Table 3-1. Endian Configuration Table BIG pin ENDCEN Status register Endian Endian Endian converter RE field in V 4120A in V 4120A in system controller operation LITTLE LITTLE Transparent LITTLE LITTLE Transparent LITTLE Data swap mode LITTLE Address swap mode Remark...
Page 203: I/O Performance
CHAPTER 3 SYSTEM CONTROLLER 3.3.6 I/O performance The following table indicates the I/O performance accessing from the V 4120A through the system controller. Target area Burst length Access latency [V 4120A clocks] IBUS target IBUS target 24-1 IBUS target 27-1-1-1 Internal register (except UART) Internal register (except UART) Invalid...
Page 204: Memory Interface
CHAPTER 3 SYSTEM CONTROLLER 3.4 Memory Interface The V 4120A accesses memory attached to the controller in the normal way, by addressing the memory space. 3.4.1 Overview • 66 MHz or 100 MHz memory bus • Supports up to 32 MB base memory range for SDRAM •...
Page 205: Memory Signal Connections
CHAPTER 3 SYSTEM CONTROLLER 3.4.3 Memory signal connections ADDRESS SMA[20:0] DATA SMD[31:0] A[20:0] D[31:0] SRMCS_B CS_B Flash SRMOE_B OE_B WE_B PROM µ µ µ µ PD98502 A[13:0] DQ[31:0] SDWE_B WE_B SDCS_B CS_B SDRAS_B RAS_B SDCAS_B CAS_B SDCKE[1:0] SDCLK[1:0] CLK[1:0] SDQM[3:0] DQM[3:0] SDRAM (SDQM=SMA[17:14])
Page 206: Memory Performance
CHAPTER 3 SYSTEM CONTROLLER 3.4.4 Memory performance The latency of memory accesses is determined by memory type, speed and prefetch scheme. Following lists some examples of access latencies. 66-MHz or 100-MHz memory-bus clock is required for each transfer of a 4-word (16- byte) CPU instruction-cache line fill.
Page 207: Rmmdr (Rom Mode Register)
CHAPTER 3 SYSTEM CONTROLLER 3.4.5 RMMDR (ROM Mode Register) The ROM mode register “RMMDR” is a read-write and 32-bit word-aligned register. RMMDR is used to setup the PROM/flash memory interface. RMMDR is initialized to 0 at reset and contains the following fields: Bits Field Default...
Page 208 CHAPTER 3 SYSTEM CONTROLLER N o rm a l R O M R e a d C yc le F L A S H M e m o ry W rite C yc le F A T (= 4) F A T (= 6) S D C L K V alid R ead Ad d ress V alid W rite Ad d ress...
Page 209: Sdmdr (Sdram Mode Register)
CHAPTER 3 SYSTEM CONTROLLER 3.4.7 SDMDR (SDRAM Mode Register) The SDRAM mode register “SDMDR” is a read-write and 32-bit word-aligned register. SDMDR is used to setup the SDRAM interface. SDMDR is initialized to 330H at reset and contains the following fields: Bits Field Default...
Page 210: Sdtsr (Sdram Type Selection Register)
CHAPTER 3 SYSTEM CONTROLLER 3.4.8 SDTSR (SDRAM Type Selection Register) The SDRAM type selection register “SDTSR” is a read-write and 32-bit word-aligned register. SDTSR is used to setup the type of SDRAM. SDTSR is initialized to 0 at reset and contains the following fields: Bits Field Default...
Page 211: Sdptr (Sdram Precharge Timing Register)
CHAPTER 3 SYSTEM CONTROLLER 3.4.9 SDPTR (SDRAM Precharge Timing Register) The SDRAM precharge timing register “SDPTR” is a read-write and 32-bit word-aligned register. SDPTR is used to set the precharge timing for the SDRAM controller. SDPTR is initialized to 142H at reset and contains the following fields: Bits Field...
Page 212: Sdrcr (Sdram Refresh Timer Count Register)
CHAPTER 3 SYSTEM CONTROLLER 3.4.11 SDRCR (SDRAM Refresh Timer Count Register) The SDRAM refresh timer count register “SDRCR” is a read-only and 32-bit word-aligned register. SDRCR is a 16- bit timer that causes an SDRAM refresh when it expires. The SDRAM refresh controller automatically reloads this free-running timer.
Page 213: Boot Rom
CHAPTER 3 SYSTEM CONTROLLER 3.4.13 Boot ROM The system controller supports up to 8 MB of boot memory. This memory must be populated with either of the following two types of memory devices: PROM/flash memory. 3.4.13.1 Boot ROM configuration and address ranges Boot ROM can be populated with PROM or 85-ns flash chips, and it must have an access time of 200 ns or less.
Page 214: Command Sequence
CHAPTER 3 SYSTEM CONTROLLER Table 3-7. Command Sequence (a) Program Command Sequence (4 Write Cycles) 1st Write 2nd Write 3rd Write 4th Write 5th Write 6th Write 1FC0_2AA8H 1FC0_1554H 1FC0_2AA8H D AAAA_AAAAH D 5555_5555H D A0A0_A0A0H D PD* (b) Chip Erase Command Sequence (6 Write Cycles) 1st Write 2nd Write 3rd Write...
Page 215 CHAPTER 3 SYSTEM CONTROLLER 3.4.1.4 Boot ROM signal connections FLASH /R O M C onfiguration E xam ple (8 M B P R O M ) E xam ple (4 M B FLA S H ) S M D [3 1 :0 ] S M D [3 1 :0 ] S M A [20:0] S M A [20:0]...
Page 216: Sdram
CHAPTER 3 SYSTEM CONTROLLER 3.4.14 SDRAM 3.4.14.1 SDRAM address range System memory can be populated with SDRAM chips, and it must have an access time of 10 ns or less. The system controller supports 16-Mbit or 64-Mbit and 128-Mbit SDRAM at locations 0000_0000H through 01FF_FFFFH in the physical memory space on V 4120A.
Page 217: Sdram Word Order For Instruction-Cache Line-Fill
CHAPTER 3 SYSTEM CONTROLLER 3.4.1.4 SDRAM word ordering Following table indicates the word-address order for a 4-word instruction-cache line fill from SDRAM. This order is determined by the SDRAM chips’ burst type, which is programmed during the memory initialization procedure. The memory controller programs the burst type and word order the same for all SDRAM chips connected to it (in the system memory ranges).
Page 218 CHAPTER 3 SYSTEM CONTROLLER S D R A M C onfiguration 4 M B S M D [15:0] S M D[31:16] DQ [15:0] DQ [15:0] S M D [31:0] S M A [11:0] S M A [11:0] A [11:0] A [11:0] S M A [13:0] W E _B W E _B...
Page 219: Sdram Refresh
CHAPTER 3 SYSTEM CONTROLLER 3.4.15 SDRAM refresh The system controller supports CAS-Before-RAS (CBR) DRAM refresh to all SDRAM address ranges. The refresh clock is derived from the system clock; its rate is determined by programming the RCR filed in the SDRAM Refresh Mode Register “SDRMR”.
Page 220: Sdram Memory Initialization
CHAPTER 3 SYSTEM CONTROLLER 3.4.18 SDRAM memory initialization The following sections describe the configuration sequence used in this initialization. 3.4.1.1 Power-on initialization sequence by memory controller The following sequence to configure memory is done automatically after reset: 1. Waits for 100 µ s after power-on. 2.
Page 221: Ibus Interface
CHAPTER 3 SYSTEM CONTROLLER 3.5 IBUS Interface 3.5.1 Overview • IBUS Master and target capability • 64-word (256-byte) IBUS Slave TxFIFO (IBUS read data from IBUS) • 64-word (256-byte) IBUS Slave RxFIFO (IBUS write data to IBUS) • 4-word (16-byte) IBUS Master TxFIFO (V 4120A read data from IBUS) •...
Page 222: Endian Conversion On Ibus Slave
CHAPTER 3 SYSTEM CONTROLLER Outline figure of Endian converter 1 byte 2 bytes word 3 bytes Big Endian: offset 0H Big Endian: offset 1H · · · · Little Endian: 0H Little Endian: 1H 3.5.3 Endian Conversion on IBUS slave “MSWP”...
Page 223: Itcntr (Ibus Timeout Timer Control Register)
CHAPTER 3 SYSTEM CONTROLLER 3.5.4 ITCNTR (IBUS Timeout Timer Control Register) The IBUS Timeout Timer control register “ITCNTR” is a read-write and word-aligned 32-bit register. ITCNTR is used to enable use of the IBUS Timeout Timer. ITCNTR is initialized to 0H at reset and contains the following field: Bits Field Default...
Page 224: Dsu (Deadman's Sw Unit)
CHAPTER 3 SYSTEM CONTROLLER 3.6 DSU (Deadman’s SW Unit) 3.6.1 Overview The DSU detects when the V 4120A is in runaway (endless loop) state and resets the V 4120A. The use of the DSU to minimize runaway time effectively minimizes data loss that can occur due to software-related runaway states. 3.6.2 DSUCNTR (DSU Control Register) This register is used to enable use of the Deadman’s Switch functions.
Page 225: Dsutimr (Dsu Elapsed Time Register)
CHAPTER 3 SYSTEM CONTROLLER 3.6.5 DSUTIMR (DSU Elapsed Time Register) This register indicates the elapsed time for the current Deadman’s Switch timer. DSUTIMR is a read-only and 32-bit word-aligned register. Default is 0H. Bits Field Default Description 31:0 CRTTIM Current Deadman’s Switch timer value (Elapsed time) example: CRTTIM = 05F5_E100H (100 MHz) or 03F9_40AAH (66 MHz) ->1 sec CRTTIM = 0BEB_C200H (100 MHz) or 07F2_8154H (66 MHz) ->...
Page 226: Endian Mode Software Issues
CHAPTER 3 SYSTEM CONTROLLER 3.7 Endian Mode Software Issues 3.7.1 Overview The native endian mode for MIPS processors, like Motorola and IBM 370 processors, is big endian. However, the native mode for Intel (which developed the PCI standard) and VAX processors is little endian. For PCI-compatibility reasons, most PCI peripheral chips operate natively in little-endian mode.
Page 227: Bit And Byte Order Of Endian Modes
CHAPTER 3 SYSTEM CONTROLLER Figure 3-1. Bit and Byte Order of Endian Modes Big End Little End Big-Endian BYTE4 BYTE5 BYTE6 BYTE7 BYTE0 BYTE1 BYTE2 BYTE3 M S B LSB = Least Significant Byte MSB = Most Significant Byte Big End Little End Little-Endian BYTE7...
Page 228: Word Data Array Example
CHAPTER 3 SYSTEM CONTROLLER However, when making half-word accesses into a data array consisting of word data, access to the more- significant half word requires the address corresponding to the less significant half word (and vice versa). Such code is not endian-independent. A super-group access (for example, accessing two half words simultaneously as a word from a half-word data array) causes the same problem.
Page 229: Chapter 4 Atm Cell Processor
CHAPTER 4 ATM CELL PROCESSOR 4.1 Overview This section describes functional specifications of ATM cell processor unit. 4.1.1 Function features Features of ATM Cell Processor with out Firmware (F/W) is as follows: • Data Transmission Capacity Aggregated transmission capacity is 50 Mbps, 25 Mbps for downstream and 25 Mbps for upstream. •...
Page 230: Block Diagram Of Atm Cell Processor
CHAPTER 4 ATM CELL PROCESSOR 4.1.2 Block diagram of ATM cell processor Figure 4-1. Block Diagram of ATM Cell Processor Ethernet 4120A RISC Controller Processor Controller #1, #2 IBUS IBUS I/F Peripherals Work REGS Data System Controller UTOPIA BUS RISC Core Controller I cache IRAM...
Page 231 CHAPTER 4 ATM CELL PROCESSOR 4.1.2.3 UTOPIA bus controller This block has some H/W resources – DMA controller, FIFOs, CRC calculators/checkers. Its features are as follows: • Scatter/Gather-DMA controller that can operate the distributed data according to descriptor tables, without F/W help.
Page 232: Atm Cell Processing Operation Overview
CHAPTER 4 ATM CELL PROCESSOR 4.1.2.4 Other blocks Work-RAM is 12 K-byte memory. Tables and Pool Descriptors are located in this RAM. It is shared between MCU and UTOPIA Bus Controller block. It also can be accessed by V 4120A RISC Processor, using Indirect-Access. 4.1.3 ATM cell processing operation overview In this section, only overview is described.
Page 233: Aal-5 Sublayer And Atm Layer
CHAPTER 4 ATM CELL PROCESSOR 4.1.3.1 AAL-5 SAR sublayer function When ATM Cell Processor transmits a cell in AAL-5 mode, it adds a trailer to the variable-length data, as well as padding, so that its overall length becomes a multiple of 48 bytes, thereby generating an AAL-5 PDU. When ATM Cell Processor receives cells, it stores them in the SDRAM in order to assemble a CPCS PDU.
Page 234: Atm Cell
CHAPTER 4 ATM CELL PROCESSOR Figure 4-4. ATM Cell Segment 48 byte header The function of each field in the header is as follows: (a) GFC (General Flow Control) field: Used for flow control. At transmission, the value set in the packet descriptor is written into this field.
Page 235: Llc Encapsulation
CHAPTER 4 ATM CELL PROCESSOR (3) Cell scheduling ATM Cell Processor uses Scheduling Table, Cell Timer and Tx VC table for the cell scheduling. Before the 4120A starts transmitting a packet, it sets the rate information in Tx VC table. ATM Cell Processor calculates cell transmission interval from the rate information, and put the next transmission time in Scheduling Table.
Page 236: Memory Space
CHAPTER 4 ATM CELL PROCESSOR 4.2 Memory Space Although the RISC Core in the ATM Cell Processor is a 32-bit MPU, its physical memory space is 24-bit width. Figure 4-6. Memory Space from V 4120A and RISC Core R IS C C ore 4120A R IS C P rocessor M em ory S pace M em ory S pace...
Page 237: Work Ram And Register Space
CHAPTER 4 ATM CELL PROCESSOR 4.2.1 Work RAM and register space Work RAM and Register Space are shown in Figure 4-7. The capacity of Work RAM is 16 KB max. In order to access Work RAM, the user has to use “Indirect Access Command”. In register space, A_GMR (general mode register), A_GSR (general status register), A_CMR (command register), A_CER (command extension register) and other registers will be mapped.
Page 238: Registers For Atm Cell Processing
CHAPTER 4 ATM CELL PROCESSOR 4.4 Registers for ATM Cell Processing Registers in ATM Cell Processor block can be classified into 3 groups: SAR registers, DMA registers and FIFO Control registers. These registers can be accessed both V 4120A and RISC Core in ATM Cell Processor. 4.4.1 Register map Registers are used for SAR functions.
Page 239 CHAPTER 4 ATM CELL PROCESSOR Offset Address Register Name Access Description 1001_F0C8H A_TSR Time Stamp Register 1001_F0CCH: Reserved for future use 1001_F1FCH 1001_F200H: Can not access from V 4120A RISC Core. 1001_F2FCH This area is used for an internal function. 1001_F300H A_IBBAR IBUS Base Address Register...
Page 240: A_Gmr (General Mode Register)
CHAPTER 4 ATM CELL PROCESSOR 4.4.2 A_GMR (General Mode Register) A_GMR is used to select operation mode of this block, enables/disables ATM SAR operations. After reset, 4120A must write this register for initialization. Modification of A_GMR after starting Tx/Rx operations is prohibited. All bits of this register are writeable, but the bits 31-15, 13-2 are reserved for future use.
Page 241: A_Imr (Interrupt Mask Register)
CHAPTER 4 ATM CELL PROCESSOR 4.4.4 A_IMR (Interrupt Mask Register) A_IMR masks interruption for each corresponding event. A Mask bit, which locates in the same bit location to a corresponding bit in A_GSR, masks interruption. If a bit of this register is reset to a ‘0’, the corresponding bit of the A_GSR is masked.
Page 242: A_Rqu (Receiving Queue Underrun Register)
CHAPTER 4 ATM CELL PROCESSOR 4.4.5 A_RQU (Receiving Queue Underrun Register) A_RQU shows the status of each pool. When a pool has no free buffers, the corresponding bit is set. ATM Cell Processor detects a pool empty when it receives a cell and try to send the cell to buffer. Whenever one of A_RQU bits is set, A_RQU bit in A_GSR will be set.
Page 243: A_Msa0 To A_Msa3 (Mailbox Start Address Register)
CHAPTER 4 ATM CELL PROCESSOR 4.4.10 A_MSA0 to A_MSA3 (Mailbox Start Address Register) A_MSA0 to A_MSA3 shows start address of Receive Mailbox (Mailbox0 and Mailbox1) and Transmit Mailbox (Mailbox2 and Mailbox3) respectively. Initial value is all zero. Bits Field Default Description 31:0 A_MSA0...
Page 244: A_Mwa0 To A_Mwa3 (Mailbox Write Address Register)
CHAPTER 4 ATM CELL PROCESSOR 4.4.13 A_MWA0 to A_MWA3 (Mailbox Write Address Register) A_MWA0 to A_MWA3 shows write address of Receive Mailbox (Mailbox0 and Mailbox1) and Transmit Mailbox (Mailbox2 and Mailbox3) respectively. Initial value is zero. Bits Default Field Description 31:0 A_MWA0 Write address of Mailbox0...
Page 245: A_T1R (T1 Time Register)
CHAPTER 4 ATM CELL PROCESSOR 4.4.18 A_T1R (T1 Time Register) A_T1R shows time which user allows ATM Cell Processor to spend to receive a whole of one packet. Initial value is “0000_FFFFH”. Bits Field Default Description Reserved Reserved for future use. Write ‘0’s. 30:0 A_T1R FFFFH...
Page 246: A_Umcmd (Utopia Management Interface Command Register)
CHAPTER 4 ATM CELL PROCESSOR 4.4.22 A_UMCMD (UTOPIA Management Interface Command Register) A_UMCMD selects operation mode of UTOPIA Management Interface. After reset, RISC Core must write this register to configure UTOPIA Management Interface. When BM bit is set to ‘0’, it means 8-bit mode and UMD [7:0] pins are valid. When BM bit is set to ‘1’, it means 16-bit mode.
Page 247: Data Structure
CHAPTER 4 ATM CELL PROCESSOR 4.5 Data Structure ATM Cell Processor has Tx/Rx buffer structure similar to that of Ethernet Controller and USB Controller. 4.5.1 Tx buffer structure The following figure shows Tx buffer structure used by ATM Cell Processor. It consists of a packet descriptor, some buffer directories, and data buffers.
Page 248: Tx Buffer Elements
CHAPTER 4 ATM CELL PROCESSOR Figure 4-9. Tx Buffer Elements - T x packet descriptor 16 15 Attribute CPCS-U U Tx buffer directory Address - T x buffer directory Tx buffer desciptor 0 Tx buffer desciptor 1 Tx buffer desciptor 2 Tx buffer desciptor 3 Tx buffer desciptor 4 Tx buffer desciptor N...
Page 249: Tx Packet Descriptor
CHAPTER 4 ATM CELL PROCESSOR 4.5.1.1 Packet descriptor A packet descriptor contains two words shown as Figure 4-10. Its address is word aligned. Figure 4-10. Tx Packet Descriptor -Tx packet descriptor 16 15 Attribute CPCS-UU CLPM C10 AAL Directory Address Table 4-1 is a list of Tx packet attributes.
Page 250: Rx Pool Structure
CHAPTER 4 ATM CELL PROCESSOR 4.5.1.2 Tx buffer directory Tx buffer directory contains some buffer descriptors, up to 255, and a link pointer. Its address is word aligned. The end of buffer directory must be a link pointer. Buffer descriptors must be read and served from the top in a sequential manner.
Page 251: Rx Pool Structure
CHAPTER 4 ATM CELL PROCESSOR Figure 4-12. Rx Pool Structure R x buffer directory D ata Size Buffer 1 to 64 kBytes R x pool0 descriptor R x buffer desc. R x pool1 descriptor R x buffer desc. D ata Buffer R x buffer desc.
Page 252: Rx Pool Descriptor/Rx Buffer Directory/Rx Buffer Descriptor/Rx Link Pointer
CHAPTER 4 ATM CELL PROCESSOR Figure 4-13. Rx Pool Descriptor/Rx Buffer Directory/Rx Buffer Descriptor/Rx Link Pointer -Rx pool descriptor 16 15 Attribute Rx buffer directory Address -Rx buffer directory Rx buffer desciptor 0 Rx buffer desciptor 1 Rx buffer desciptor 2 Rx buffer desciptor 3 Rx buffer desciptor 4 Rx buffer desciptor 5...
Page 253: Rx Pool Descriptor
CHAPTER 4 ATM CELL PROCESSOR 4.5.2.1 Rx pool descriptor A pool descriptor contains two words shown as Figure 4-14. Its address is word aligned. Figure 4-14. Rx Pool Descriptor -R x pool descrip tor 31 30 28 27 24 23 16 15 all 0 dir.
Page 254: Rx Buffer Descriptor/ Link Pointer
CHAPTER 4 ATM CELL PROCESSOR Figure 4-15. Rx Buffer Descriptor/ Link Pointer -Rx buffer descriptor 31 30 16 15 Attribute Size Buffer Address -Rx link pointer 31 30 16 15 Reserved Directory Address 4.5.2.4 Rx data buffer Rx Data buffer contains actual received cell data. Size of a buffer can vary from 1 byte to 64 kbytes. Its address is byte aligned.
Page 255: Initialization
CHAPTER 4 ATM CELL PROCESSOR 4.6 Initialization This ATM Cell Processor is initialized by firmware that is based RISC instruction. 4.6.1 Before starting RISC core RISC Core has 1 MB of Instruction space and 8 KB of physical Instruction RAM and 8 KB of instruction cache. The Instruction space will be mapped to the external system memory space.
Page 256: After Risc Core's F/W Is Starting
CHAPTER 4 ATM CELL PROCESSOR 4.6.2 After RISC core’s F/W is starting RISC Core starts its operation from address xx00_0000H. When it starts fetching an instruction located in address xx00_0000H, a dedicated H/W will stop RISC Core and will copy a block of instructions. This copy operation will be handled in the same manner as I-cache replacement.
Page 257: Commands
CHAPTER 4 ATM CELL PROCESSOR 4.7 Commands Here, basic commands used in AAL-5 operation are described. Other commands used in AAL-2, OAM and cell switching functions are described in µ µ µ µ PD98502 Application Note (to be planned). ATM Cell Processor provides V 4120A with the following basic commands.
Page 258: Set_Link_Rate Command
CHAPTER 4 ATM CELL PROCESSOR 4.7.1 Set_Link_Rate command This command is used to set the link rate of ATM PHY interface. After initializing ATM Cell Processor, this command has to be issued once, before any packet is transmitted. Figure 4-18. Set_Link_Rate Command [Set_Link_Rate command] PHY No.
Page 259: Close_Channel Command
CHAPTER 4 ATM CELL PROCESSOR 4.7.3 Close_Channel command The Close_Channel command is used to close a send or receive channel. Upon accepting this command, ATM Cell Processor returns the VC table to VC Table pool. The indication that ATM Cell Processor returns for this command has the following format: Figure 4-20.
Page 260: Tx_Ready Command
CHAPTER 4 ATM CELL PROCESSOR 4.7.4 Tx_Ready command The Tx_Ready command is used by the V 4120A to notify ATM Cell Processor that a transmit packet has been added for a specified channel (a new packet descriptor has been set in system memory queue). Upon receiving this command, ATM Cell Processor makes the scheduling table active to perform scheduling.
Page 261: Add_Buffers Command
CHAPTER 4 ATM CELL PROCESSOR 4.7.5 Add_Buffers command The Add_Buffers command is used to add unused buffer directories to a single receive free buffer pool. In this command, when ATM Cell Processor detects some errors, it writes E bit in A_CMR. This command has the following format: Figure 4-22.
Page 262: Indirect_Access Command
CHAPTER 4 ATM CELL PROCESSOR 4.7.6 Indirect_Access command The Indirect_Access command is used to perform read/write access to Work RAM. Figure 4-23. Indirect_Access Command [Indirect_Access command] R/W B3 B2 B1 B0 Address 29 28 27 26 25 24 23 Data Indirect_Access command Specifies whether access to the target is a read or a write access.
Page 263: Transmission Function
CHAPTER 4 ATM CELL PROCESSOR Figure 4-24. Work RAM Usage W o rk R A M (1 0 K b yte s ) xx80_3F FF H T em porary D ata xx80_1840H Pack et Info Structure Pool 1024 bytes (4 W ords x 64) xx80_1440H Flow T able P ool 1024 bytes...
Page 264 CHAPTER 4 ATM CELL PROCESSOR 4.8.2.1 Transmission procedure (a) Setting transmitting data Before transmitting a packet, V 4120A places a packet data to be sent in system memory and sets the packet descriptor. (b) Opening the send channel If V 4120A needs a new channel for transmitting of the packet data, V 4120A issues Open_Channel command.
Page 265: Structure Of The Transmit Queue
CHAPTER 4 ATM CELL PROCESSOR 4.8.2.2 Transmit queue Tx_Ready command has to be issued in order to transmit a packet. However, V 4120A doesn’t have to wait Tx indication before issuing next Tx_Ready command for the same VC. When V 4120A issues Tx_Ready command before completing transmission process for the previous packet, ATM Cell Processor builds Tx Queue for that VC.
Page 266: Transmit Queue Packet Descriptor
CHAPTER 4 ATM CELL PROCESSOR (2) Packet descriptor Figure 4-27. Transmit Queue Packet Descriptor 0 ENC CLPM IM C10 AAL MB CPCS-UU 31 30 29 28 27 26 24 23 20 19 18 17 16 15 Buffer Directory Address Encapsulation mode is indicated. LLC encapsulation No encapsulation CLPM...
Page 267: Tx Vc Table
CHAPTER 4 ATM CELL PROCESSOR (3) Tx VC table Figure 4-28. Tx VC Table Word 0 ENC CLPM IM C10 AAL MB CPSS-UU 31 30 29 28 27 26 24 23 20 19 18 17 16 15 Word 1 PRIORITY VPI/VCI 31 30 27 26...
Page 268 CHAPTER 4 ATM CELL PROCESSOR Word0 Identical to the contents of Word0 in the packet descriptor in system memory. The initial value must be all zeros. ATM Cell copies the Word0 in the packet descriptor into this field. This bit is used internally for SAR processing. The initial value must always be a 1. PRIORITY Specifies send priority.
Page 269: Raw Cell With Crc-10
CHAPTER 4 ATM CELL PROCESSOR (2) Raw cell transmission When host sends the non AAL-5 traffic packet which is not OAM F5 cell, host sets “AAL” bit in the packet descriptor to a 0 and “PTI” field “0xx” which indicates user data. In this case, ATM Cell Processor doesn’t calculate or add AAL-5 trailer.
Page 270: Receiving Function
CHAPTER 4 ATM CELL PROCESSOR 4.8.2.6 LLC encapsulation If LLC encapsulation is indicated in Tx VC table, ATM Cell Processor adds the LLC header to the top of the IP packet. ATM Cell Processor always encapsulates CPCS-PDU as Internet IP PDU. Figure 4-31.
Page 271: Receive Vc Table
CHAPTER 4 ATM CELL PROCESSOR (1) Rx VC table Figure 4-32. Receive VC Table Word 0 CLP BFA 0 RID DD DP 0 CI OD A/R MB POOL No. UINFO 31 30 29 28 27 26 25 24 23 22 21 20 16 15 Word 1 T1 TIME STAMP...
Page 272 CHAPTER 4 ATM CELL PROCESSOR Set to a 1 if the CLP in the header of at least one cell of the packets being received is equal to a 1. Set to a 1 if the free buffer assigned to this VC exists. Set to a 1 if an error occurs while a packet is being received.
Page 273: Raw Cell Data Format
CHAPTER 4 ATM CELL PROCESSOR Figure 4-33. Raw Cell Data Format WORD0 CELL HEADER WORD1 BYTE2 BYTE1 BYTE0 WORD12 BYTE46 BYTE45 BYTE44 BYTE43 WORD13 UINFO BYTE47 WORD14 TIME STAMP WORD15 VC NUMBER Cell Header Header of the cell except HEC. HEC field pattern of the cell.
Page 274: Receive Indication Format
CHAPTER 4 ATM CELL PROCESSOR Figure 4-34. Receive Indication Format UINFO PACKET SIZE 16 15 TIME STAMP PACKET START ADDRESS VC Number ERR CI C LP 0 ERR STATUS POOL No. 31 30 16 15 14 13 12 11 UINFO Pattern set by the host in the UINFO field in the VC table PACKET SIZE Size of the receive packet in cell units...
Page 275: Reception Errors That Can Occur During Packet Reception
CHAPTER 4 ATM CELL PROCESSOR (2) Max No. of bytes violation This error occurs if the last cell of a packet has not been received when the number of cells received has reached the user-specified "Max. No. of bytes" When the next cell is received, the RID bit is set and a receive indication is issued.
Page 276: Mailbox
CHAPTER 4 ATM CELL PROCESSOR 4.8.4 Mailbox ATM Cell Processor uses mailboxes as ring buffers in system memory. The structure of a mailbox and the defined addresses are as follows. Mailbox start address (A_MSA[3:0]) :The start address of the mailbox Mailbox bottom address (A_MBA[3:0]) :The bottom address of the mailbox (address following the last address) Mailbox write address (A_MWA[3:0])
Page 277: Chapter 5 Ethernet Controller
CHAPTER 5 ETHERNET CONTROLLER 5.1 Overview This section describes Ethernet Controller block. This Ethernet Controller block comprises of a 10/100 Mbps Ethernet MAC (Media Access Control), data transmit/receive FIFOs, DMA and internal bus interface. The µ PD98502 implements 2-channel Ethernet Controller. 5.1.1 Features •...
Page 278: Block Diagram Of Ethernet Controller
CHAPTER 5 ETHERNET CONTROLLER Figure 5-1. Block Diagram of Ethernet Controller Ethernet Controller Block IBUS Transceiver FIFO TPO+ TPO– Core TPI+ FIFO TPI– FIFO Cont. µ µ µ µ PD98502 Preliminary User’s Manual S15543EJ1V0UM...
Page 279: Registers
CHAPTER 5 ETHERNET CONTROLLER 5.2 Registers Registers of this block are categorized following four categories as shown in Table 5-1. 4120A controls following registers. The µ PD98502 has 2-channel Ethernet Controller, #1 controller’s base address is 1000_2000H, #2 controller’s base address is 1000_3000H. Table 5-1.
Page 280 CHAPTER 5 ETHERNET CONTROLLER Offset Address Register Name Access Description 1000_m0A8H: Reserved for future use 1000_m0C4H 1000_m0C8H En_AFR Address Filtering Register 1000_m0CCH En_HT1 Hash Table Register 1 1000_m0D0H En_HT2 Hash Table Register 2 1000_m0D4H: Reserved for future use 1000_m0D8H 1000_m0DCH En_CAR1 Carry Register 1 1000_m0E0H...
Page 281: Statistics Counter Register Map
CHAPTER 5 ETHERNET CONTROLLER Table 5-3. Statistics Counter Register Map Offset Address Register Name Access Description 1000_m140H En_RBYT Receive Byte Counter 1000_m144H En_RPKT Receive Packet Counter 1000_m148H En_RFCS Receive FCS Error Counter 1000_m14CH En_RMCA Receive Multicast Packet Counter 1000_m150H En_RBCA Receive Broadcast Packet Counter 1000_m154H En_RXCF...
Page 282 CHAPTER 5 ETHERNET CONTROLLER Offset Address Register Name Access Description 1000_m1C4H En_TPCT Transmit Packet Counter 1000_m1C8H En_TFCS Transmit CRC Error Packet Counter 1000_m1CCH En_TMCA Transmit Multicast Packet Counter 1000_m1D0H En_TBCA Transmit Broadcast Packet Counter 1000_m1D4H En_TUCA Transmit Unicast Packet Counter 1000_m1D8H En_TXPF Transmit PAUSE control Frame Counter...
Page 283: Dma And Fifo Management Registers Map
CHAPTER 5 ETHERNET CONTROLLER 5.2.1.3 DMA and FIFO management registers These registers control to transfer receive and transmit data by internal DMAC of this block. Table 5-4. DMA and FIFO Management Registers Map Offset Address Register Name Access Description 1000_m200H En_TXCR Transmit Configuration Register 1000_m204H...
Page 284: Interrupt And Configuration Registers Map
CHAPTER 5 ETHERNET CONTROLLER 5.2.1.4 Interrupt and configuration registers These register control interrupt occur and configuration for this block. Table 5-5. Interrupt and Configuration Registers Map Offset Address Register Name Access Description 1000_m234H En_CCR Configuration Register 1000_m238H En_ISR Interrupt Service Register 1000_m23CH En_MSR Mask Serves Register...
Page 285: En_Macc1 (Mac Configuration Register 1)
CHAPTER 5 ETHERNET CONTROLLER 5.2.2 En_MACC1 (MAC Configuration Register 1) Bits Field Default Description 31:12 Reserved Reserved for future use. Write 0s. TXFC Transmit flow control enable: Setting this bit to a ‘1’ enables to transmit the pause control frame. RXFC Receive flow control enable: Setting this bit to a ‘1’...
Page 286: En_Macc2 (Mac Configuration Register 2)
CHAPTER 5 ETHERNET CONTROLLER 5.2.3 En_MACC2 (MAC Configuration Register 2) Bits Field Default Description 31:11 Reserved Reserved for future use. Write 0s. MCRST MAC Control Block software reset: Setting this bit to a ‘1’ forces MAC Control Block to a software reset operation.
Page 287: En_Clrt (Collision Register)
CHAPTER 5 ETHERNET CONTROLLER 5.2.6 En_CLRT (Collision Register) Bits Field Default Description 31:14 Reserved Reserved for future use. Write 0s. 13:8 LCOL Late collision window: This field sets collision window size. The formula for the collision window size is: collision window size = (LCOL + 8) × 8 bits time Reserved Reserved for future use.
Page 288: En_Ptvr (Pause Timer Value Read Register)
CHAPTER 5 ETHERNET CONTROLLER 5.2.11 En_PTVR (Pause Timer Value Read Register) Bits Field Default Description 31:16 Reserved Reserved for future use. 15:0 PTCT Pause timer counter: This field indicates the current pause timer value. 5.2.12 En_VLTP (VLAN Type Register) Bits Field Default Description...
Page 289: En_Madr (Mii Address Register)
CHAPTER 5 ETHERNET CONTROLLER 5.2.15 En_MADR (MII Address Register) Bits Field Default Description 31:13 Reserved Reserved for future use. Write 0s. 12:8 FIAD MII PHY address: This field sets PHY address to be selected during the management access. Reserved Reserved for future use. Write 0s. RGAD MII register address: This field sets register address to be accessed during the management...
Page 290: En_Afr (Address Filtering Register)
CHAPTER 5 ETHERNET CONTROLLER 5.2.19 En_AFR (Address Filtering Register) Bits Field Default Description 31:4 Reserved Reserved for future use. Write 0s. Promiscuous mode: When this bit is set to a ‘1’, all receive packets are accepted. Please refer to 5.3.6. Accept Multicast: When this bit is set to a ‘1’, all multicast packets are accepted.
Page 291: En_Car1 (Carry Register 1)
CHAPTER 5 ETHERNET CONTROLLER 5.2.22 En_CAR1 (Carry Register 1) The bits of this register indicate that an overflow event has occurred in statistics counters. Each bit corresponds to a counter, and the bit is set to a ‘1’ when the corresponding statistics counter overflow event occurs. Bits Field Default...
Page 292: En_Car2 (Carry Register 2)
CHAPTER 5 ETHERNET CONTROLLER 5.2.23 En_CAR2 (Carry Register 2) The bits of this register indicate that an overflow event has occurred in statistics counters. Each bit corresponds to a counter, and the bit is set to a ‘1’ when the corresponding statistics counter overflow event occurs. Bits Field Default...
Page 293: En_Cam1 (Carry Register 1 Mask Register)
CHAPTER 5 ETHERNET CONTROLLER 5.2.24 En_CAM1 (Carry Register 1 Mask Register) This register masks the Interrupt that is generated from the setting of the bits in the En_CAR1 register. Each mask bit can be enabled independently. Bits Field Default Description 31:16 Reserved Reserved for future use.
Page 294: En_Cam2 (Carry Register 2 Mask Register)
CHAPTER 5 ETHERNET CONTROLLER 5.2.25 En_CAM2 (Carry Register 2 Mask Register) This register masks the Interrupt that is generated from the setting of the bits in the En_CAR2 register. Each mask bit can be enabled independently. Bits Field Default Description M2XD Status vector overrun mask bit 30:23...
Page 295: En_Txfcr (Transmit Fifo Control Register)
CHAPTER 5 ETHERNET CONTROLLER 5.2.27 En_TXFCR (Transmit FIFO Control Register) Bits Field Default Description 31:16 TPTV FFFFH Transmit Pause Timer Value: 15:10 TX_DRTH Transmit Drain Threshold Level: This threshold is enable to the transmit data to the MAC Control Block form the Tx-FIFO.
Page 296: En_Txdpr (Transmit Descriptor Pointer)
CHAPTER 5 ETHERNET CONTROLLER 5.2.28 En_TXDPR (Transmit Descriptor Pointer) Bits Field Default Description 31:2 XMTDP Transmit Descriptor Please see the Section 5.3.4 Reserved Reserved for future use. Write 0s. 5.2.29 En_RXCR (Receive Configuration Register) Bits Field Default Description Receive Enable: 0: Disable 1: Enable 30:19...
Page 297: En_Rxfcr (Receive Fifo Control Register)
CHAPTER 5 ETHERNET CONTROLLER 5.2.30 En_RXFCR (Receive FIFO Control Register) Bits Field Default Description 31:26 Upper Water Mark: [7:2] This pointer is used with Auto Flow Control Enable bit in En_TXCR. When the receiving data fill level exceeds this pointer, the transmit module generates a flow control frame automatically.
Page 298: En_Rxpdr (Receive Pool Descriptor Pointer)
CHAPTER 5 ETHERNET CONTROLLER 5.2.32 En_RXPDR (Receive Pool Descriptor Pointer) Bits Field Default Description Reserved Reserved for future use. Write a 0. 30:28 AL[2:0] Alert Level 27:16 Reserved Reserved for future use. Write 0s. 15:0 RNOD Remaining Number of Descriptor [15:0] 5.2.33 En_CCR (Configuration Register) Bits...
Page 299: En_Msr (Mask Serves Register)
CHAPTER 5 ETHERNET CONTROLLER 5.2.35 En_MSR (Mask Serves Register) Each interrupt source is maskable. En_MSR register shows which interrupts are enable. Default value is all “0” which means all interrupt sources are disable. Bits Field Default Description 31:16 Reserved Reserved for future use. Write 0s. XMTDN Transmit Done TBDR...
Page 300: Operation
CHAPTER 5 ETHERNET CONTROLLER 5.3 Operation 5.3.1 Initialization After a power on reset or a software reset, V 4120A has to set the following registers: i) Interrupt Mask Registers ii) Configuration Registers iii) MII Management Registers iv) Pool/Buffer Descriptor Registers 5.3.2 Buffer structure for Ethernet Controller block The data buffer structure for Ethernet Controller is shown in Figure 5-4.
Page 301: Buffer Descriptor Format
CHAPTER 5 ETHERNET CONTROLLER 5.3.3 Buffer descriptor format The Transmit Descriptor format is shown in Figure 5-5 and the description is shown in Table 5-6. Figure 5-5. Transmit Descriptor Format Word 0 Attribute Size Word 1 Buffer Address Pointer Table 5-6. Attribute for Transmit Descriptor Attribute &...
Page 302: Frame Transmission
CHAPTER 5 ETHERNET CONTROLLER Table 5-7. Attribute for Receive Descriptor Attribute & Size Bit Name Status Last Descriptor Data Buffer / Link Pointer Owner bit 1:Ethernet Controller 0: V 4120A Ethernet Controller sets this bit after it began to transfer data into each descriptor.
Page 303 CHAPTER 5 ETHERNET CONTROLLER Short frames are automatically padded by the transmit logic if PADEN bit in En_MACC1 register is set. If the transmit frame length exceeds 1518 bytes, Ethernet Controller will assert an interrupt. However, the entire frame will be transmitted (no truncation).
Page 304: Transmit Procedure
CHAPTER 5 ETHERNET CONTROLLER Figure 5-7. Transmit Procedure 4120A Ethernet Controller External PHY Device Initialize Registers Initialize Link Configuration Auto Negotiation Prepare Buffer Descriptors Transmit Data Set XMDP Transmit Descriptor address Set TXE Set Transmit Enable Get transmit data Exceed TXDRTH Carrier Sense Carrier Sense Send...
Page 305: Frame Reception
CHAPTER 5 ETHERNET CONTROLLER Operation flow for transmit packet i) Prepares transmit data in data buffer ii) Initializes registers (XMDP, TXE) iii) Reads buffer descriptor for transmission from SDRAM iv) Reads transmit data from data buffer by using master DMA burst operation v) Waits for exceeding of transmit drain threshold (TXDRTH) Senses carrier Transmits data (Preamble.
Page 306: Receive Procedure
CHAPTER 5 ETHERNET CONTROLLER When the receive frame is complete, Ethernet Controller sets the L-bit in the Receive Descriptor, writes the frame status bits into the Receive Descriptor, and sets the OWN-bit. Ethernet Controller generates a maskable interrupt, indicating that a frame has been received and is in memory. Ethernet Controller then waits for a new frame. Receive procedure is as follows: (Figure 5-8) Figure 5-8.
Page 307: Address Filtering
CHAPTER 5 ETHERNET CONTROLLER Operation flow for receive packet i) Prepares the receive buffer descriptors ii) Initializes registers (RXVDP, RXE) iii) Reads the receive buffer descriptor iv) Waits for exceeding of receive drain threshold (RXDRTH) v) Writes receive data to data buffer by using master DMA burst operation vi) Increments the Receive Descriptor Pointer if the current data buffer is full vii) Check out the RNOD If the remaining number of descriptors is less than four times of the alert level, generates an interrupt to...
Page 308 CHAPTER 5 ETHERNET CONTROLLER (3) Broadcast address filtering All of received packets with broadcast destination address are received when ABC bit in En_AFR register is set to a ‘1’. (4) Promiscuous mode Setting PRO bit in En_AFR register to a ‘1’ caused all of received packets to be received. Filtering procedure is as follows: At first, SRXEN bit in En_MACC1 register is set to a ‘1’.
Page 309: Chapter 6 Usb Controller
CHAPTER 6 USB CONTROLLER 6.1 Overview The USB Controller handles the data communication through USB. The following lists the features of USB Controller. 6.1.1 Features • Conforms to Universal Serial Bus Specification Rev 1.1 • Supports operation conforming to the USB Communication Device Class Specification •...
Page 310: Internal Block Diagram
CHAPTER 6 USB CONTROLLER 6.1.2 Internal block diagram USB Controller internal block diagram is as shown below. Figure 6-1. USB Controller Internal Configuration IB U S U S B C O N TR O LLE R M C O N T B U S I/F M aster Tx FIFO...
Page 311: Registers
CHAPTER 6 USB CONTROLLER 6.2 Registers This section explains the mapping of those registers that can be accessed from IBUS. USB base address is 1000_1000H 6.2.1 Register map Offset Address Register Name Access Description 1000_1000H U_GMR W/H/B USB General Mode Register 1000_1004H U_VER W/H/B...
Page 312 CHAPTER 6 USB CONTROLLER 2. All internal registers are 32-bit word-aligned registers. 3. The burst access to the internal register is prohibited. If such burst access has been occurred, IRERR bit in NSR is set and NMI will assert to CPU. 4.
Page 313: U_Gmr (Usb General Mode Register)
CHAPTER 6 USB CONTROLLER 6.2.2 U_GMR (USB General Mode Register) This register is used for setting the operation of USB Controller. The low-order sixteen bits except for RR bit can be written only when the device is being initialized. If the values of these bits are changed while transmission or reception is being performed, the operation of USB Controller may become unpredictable.
Page 314: U_Gsr1 (Usb General Status Register 1)
CHAPTER 6 USB CONTROLLER 6.2.4 U_GSR1 (USB General Status Register 1) This register indicates the current status of USB Controller. Bits Field Default Description GSR2 If some bits of General Status Register 2 are set to ‘1’s and the corresponding bits in Interrupt Mask Register 2 are set to ‘1’s, this GSR2 bit will be set to a ‘1’.
Page 315 CHAPTER 6 USB CONTROLLER Bits Field Default Description EP1FU EP1 FIFO Error: Bit that indicates that an underrun has occurred for the FIFO of EndPoint1 (Isochronous IN). When the FIFO empties while EndPoint1 is performing a transaction, this bit is set to a ‘1’. This bit is reset to a ‘0’...
Page 316: U_Imr1 (Usb Interrupt Mask Register 1)
CHAPTER 6 USB CONTROLLER 6.2.5 U_IMR1 (USB Interrupt Mask Register 1) This register is used to mask interrupts. When a bit in this register is set to a ‘1’ and the corresponding bit in the USB General Status Register 1 (Address: 10H) is set to a ‘1’, an interrupt is issued.
Page 317 CHAPTER 6 USB CONTROLLER Bits Field Default Description EP3TF EP3 Tx Finished: 1 = unmask. 0 = mask. EP2RF EP2 Rx Finished: 1 = unmask. 0 = mask. EP1TF EP1 Tx Finished: 1 = unmask. 0 = mask. EP0RF EP0 Rx Finished: 1 = unmask.
Page 318: U_Gsr2 (Usb General Status Register 2)
CHAPTER 6 USB CONTROLLER 6.2.6 U_GSR2 (USB General Status Register 2) This register indicates the current status of USB Controller. Reading this register clears all bits in this register. Bits Field Default Description 31:21 Reserved Reserved for future use Frame Number Written: This bit is set to a ‘1’...
Page 319: U_Imr2 (Usb Interrupt Mask Register 2)
CHAPTER 6 USB CONTROLLER 6.2.7 U_IMR2 (USB Interrupt Mask Register 2) This register is used to mask interrupts. When a bit in this register is set to a ‘1’ and the corresponding bit in the USB General Status Register 2 (Address: 18H) is set to a ‘1’, GSR2 bit in the U_GSR1 will be set to a ‘1’.
Page 320: U_Ep0Cr (Usb Ep0 Control Register)
CHAPTER 6 USB CONTROLLER 6.2.8 U_EP0CR (USB EP0 Control Register) This register is used for setting the operation of EndPoint0. If the value in the MAXP field is rewritten during transmitting or receiving operation, the operation of USB Controller may become unpredictable. Therefore, the MAXP can be written only when initial setting is being performed. Bits Field Default...
Page 321: U_Ep1Cr (Usb Ep1 Control Register)
CHAPTER 6 USB CONTROLLER 6.2.9 U_EP1CR (USB EP1 Control Register) This register is used for setting the operation of EndPoint1. If the value in the MAXP field is rewritten during transmitting operation, the operation of USB Controller may become unpredictable. Therefore, the MAXP can be written only when initial setting is being performed. Bits Field Default...
Page 322: U_Ep3Cr (Usb Ep3 Control Register)
CHAPTER 6 USB CONTROLLER 6.2.11 U_EP3CR (USB EP3 Control Register) This register is used for setting the operation of EndPoint3. If the value in the MAXP field is rewritten during transmitting operation, the operation of USB Controller may become unpredictable. Therefore, the MAXP can be written only when initial setting is being performed. Bits Field Default...
Page 323: U_Ep4Cr (Usb Ep4 Control Register)
CHAPTER 6 USB CONTROLLER 6.2.12 U_EP4CR (USB EP4 Control Register) This register is used for setting the operation of EndPoint4. If the value in the MAXP field is rewritten during receiving operation, the operation of USB Controller may become unpredictable. Therefore, the MAXP can be written only when initial setting is being performed. Bits Field Default...
Page 324: U_Ep5Cr (Usb Ep5 Control Register)
CHAPTER 6 USB CONTROLLER 6.2.13 U_EP5CR (USB EP5 Control Register) This register is used for setting the operation of EndPoint5. If the value in the MAXP field is rewritten during transmitting operation, the operation of USB Controller may become unpredictable. Therefore, the MAXP can be written only when initial setting is being performed. Bits Field Default...
Page 325: U_Cmr (Usb Command Register)
CHAPTER 6 USB CONTROLLER 6.2.15 U_CMR (USB Command Register) This register is used for issuing Tx request or adding Rx Buffer Directories to Pool. The V 4120A writes commands into this register. Whenever B bit (Bit 31) is set, the value will not change even if the V 4120A writes commands into this register.
Page 326: U_Tepsr (Usb Tx Endpoint Status Register)
CHAPTER 6 USB CONTROLLER 6.2.17 U_TEPSR (USB Tx EndPoint Status Register) This register is used for indicate the status of the EndPoint being used for data transmitting. Bits Field Default Description 31:26 Reserved Reserved for future use 25:24 EP5TS EP5 Tx Status: Register that indicates the transmit status of EndPoint5 This register is not cleared, even if read.
Page 327: U_Rp0Ar (Usb Rx Pool0 Address Register)
CHAPTER 6 USB CONTROLLER 6.2.19 U_RP0AR (USB Rx Pool0 Address Register) This register indicates the start address of Buffer Directory which is currently used. The way to set up Rx Pool is described at Section 6.6.3 Receive pool settings. Bits Field Default Description...
Page 328: U_Rp2Ir (Usb Rx Pool2 Information Register)
CHAPTER 6 USB CONTROLLER 6.2.22 U_RP2IR (USB Rx Pool2 Information Register) This register indicates the information of Receive Pool2. The V 4120A writes to this register only when the device is being initialized. Bits Field Default Description Reserved Reserved for future use. Writes ‘0’s. 30:28 Alert Level: Sets the warning level for Pool0.
Page 329: U_Tmwa (Usb Tx Mailbox Write Address Register)
CHAPTER 6 USB CONTROLLER 6.2.27 U_TMWA (USB Tx MailBox Write Address Register) Bits Field Default Description 31:0 Address Register that indicates the address in the transmit MailBox area to which USB Controller will write next time. 6.2.28 U_RMSA (USB Rx MailBox Start Address Register) Bits Field Default...
Page 330: Usb Attachment Sequence
CHAPTER 6 USB CONTROLLER 6.3 USB Attachment Sequence This section describes the sequence that is followed when the µ PD98502 is attached to a USB hub. Figure 6-2. USB Attachment Sequence H ost P C U S B 4120A C ontroller C onnect to a H U B T he H U B detects that a new device is...
Page 331: Initialization
CHAPTER 6 USB CONTROLLER 6.4 Initialization After USB Controller has been reset, the V 4120A must set several USB Controller registers. The initialization sequence is listed below. (1) A desired mode is set into the USB General Mode Register. (2) The receive pools are placed in system memory, and the information they contain are set in the following registers: USB Rx Pool0 Information Register: (Address: 1000_1050H)
Page 332: Receive Pool Settings
CHAPTER 6 USB CONTROLLER 6.4.1 Receive pool settings For details of the receive pool settings, see Section 6.6.3 Receive pool settings. 6.4.2 Transmit/receive MailBox settings After USB Controller transmits a data segment, it indicates the status by writing a transmit indication in ‘MailBox’ in system memory.
Page 333: Mailbox Configuration
CHAPTER 6 USB CONTROLLER Figure 6-3. Mailbox Configuration U_TMSA(U_RMSA) U_TMRA(U_RMRA) U_TMWA(U_RMWA) U_TMBA(U_RMBA) When USB Controller writes an indication, the write pointer (U_TMWA or U_RMWA) is incremented. Every time that USB Controller writes an indication, it also sets the transmit/receive finish bit of the corresponding EndPoint and, issues an interrupt if it is not masked.
Page 334: Data Transmit Function
CHAPTER 6 USB CONTROLLER 6.5 Data Transmit Function This section explains USB Controller's data transmit function. 6.5.1 Overview of transmit processing USB Controller divides the data segments in system memory, into USB packets, then transmits them to the Host PC. The V 4120A sets the size of USB packet in the MAXP field of the EP0 Control Register, the EP1-2 Control Register, the EP3-4 Control Register, and the EP5-6 Control Register (in the example shown below, a value of 64 bytes has been set).
Page 335: Tx Buffer Configuration
CHAPTER 6 USB CONTROLLER Figure 6-5. Tx Buffer Configuration Tx Packet Buffer Directory Data Buffer Buffer descriptor Buffer descriptor Data Buffer Buffer descriptor Link pointer Data Buffer Buffer descriptor Data Buffer Buffer desc.(L=1) Data Buffer A transmit packet is configured by breaking up multiple data buffers in system memory. These data buffers are bundled together in the buffer directory.
Page 336: Configuration Of Transmit Buffer Directory
CHAPTER 6 USB CONTROLLER Figure 6-6. Configuration of Transmit Buffer Directory -Tx Buffer D irectory B uffer D escriptor 0 B uffer D escriptor 1 B uffer D escriptor 2 B uffer D escriptor 3 B uffer D escriptor 4 B uffer D escriptor N Link P ointer -Tx Buffer D escriptor...
Page 337: Data Transmit Modes
CHAPTER 6 USB CONTROLLER 6.5.3 Data transmit modes USB Controller supports two transmit modes. These modes differ only in whether a zero-length USB packet is transmitted after the last USB packet of a data segment. In all other aspects, they are identical. The transmit mode is switched using the TM bit (Bit 19) of the USB EP1 EndPoint Control Register (Address: 1000_1024H) and USB EP3 EndPoint Control Register (Address: 1000_102CH).
Page 338: R 4120A Processing At Data Transmitting
CHAPTER 6 USB CONTROLLER 6.5.4 V 4120A processing at data transmitting This section explains the processing performed by the V 4120A when transmitting data. Figure 6-7. V 4120A Processing at Data Transmitting Prepare Tx data in the memory Reads U SB Command R egister Busy bit = "1"...
Page 339: Transmit Command Issue
CHAPTER 6 USB CONTROLLER First, the V 4120A prepares the data to be transmitted in system memory. The V 4120A reads the USB Command Register. The V 4120A checks whether the Busy bit of the USB Command Register is set. If the Busy bit is set, it indicates that USB Controller is still executing the previous command.
Page 340: Transmit Status Register
CHAPTER 6 USB CONTROLLER Figure 6-9. Transmit Status Register USB Tx EndPoint Status Register (48H) Corresponding to each EndPoint 00: Idle 01: Sending one data 10: Sending two data (Busy) Preliminary User’s Manual S15543EJ1V0UM...
Page 341: Usb Controller Processing At Data Transmitting
CHAPTER 6 USB CONTROLLER 6.5.5 USB controller processing at data transmitting This section presents all of the processing performed by USB Controller at data transmitting. Figure 6-10. USB Controller Transmit Operation Flow Chart T x co m m and is set S et US B Com m and R egister B usy bit to "1".
Page 342 CHAPTER 6 USB CONTROLLER Numbers (1) to (15) do not indicate the order in which USB Controller must perform processing. Instead, these numbers correspond to those in the following explanation. USB Controller starts transmit processing upon receiving a transmit command from the V 4120A.
Page 343: Tx Indication
CHAPTER 6 USB CONTROLLER 6.5.6 Tx indication For every data segment to be transmitted, USB Controller writes a Tx indication into the Tx MailBox. After writing a Tx indication, USB Controller sets the transmit completion bit of USB General Status Register1 to 1 and, provided it is not masked, issues an interrupt to the V 4120A.
Page 344: Data Receive Function
CHAPTER 6 USB CONTROLLER 6.6 Data Receive Function This section explains USB Controller's data receive function. 6.6.1 Overview of receive processing USB Controller receives USB packets from the USB, stores them into system memory, and then assembles a single data segment. The V 4120A sets the size of a single USB packet in the MAXP field of the EP0 Control Register, EP1-2 Control Register, EP3-4 Control Register, and EP5-6 Control Register.
Page 345: Rx Buffer Configuration
CHAPTER 6 USB CONTROLLER 6.6.2 Rx Buffer configuration Data received from the USB is stored into a receive pool in system memory. USB Controller uses three receive pools. The configuration of the receive pools is shown below. Figure 6-13. Receive Buffer Configuration B uffer D irectory D ata Size...
Page 346: Receive Descriptor Configuration
CHAPTER 6 USB CONTROLLER Figure 6-14. Receive Descriptor Configuration -R x Buffer D irectory B uffer D esciptor 0 B uffer D esciptor 1 B uffer D esciptor 2 B uffer D esciptor 3 B uffer D esciptor 4 B uffer D esciptor N Link P ointer -R x Buffer D escriptor 16 15...
Page 347: Receive Pool Settings
CHAPTER 6 USB CONTROLLER 6.6.3 Receive pool settings USB Controller uses three receive pools. Pool0 For EndPoint0 (Control) and EndPoint6 (Interrupt) Pool1 For EndPoint2 (Isochronous) Pool2 For EndPoint4 (Bulk) The data in each of these three pools is written into the corresponding registers. Pool0 USB Rx Pool0 Information Register (Address: 1000_1050H)
Page 348: Data Receive Mode
CHAPTER 6 USB CONTROLLER (a) If any unused Buffer Directories remain in the pool (when the RNOD field in the Pool Information Register is set to grater than 0), USB Controller adds the number in the NOD field of the command to the RNOD field of the Pool Information Register.
Page 349: Data Receiving In Endpoint0, Endpoint6
CHAPTER 6 USB CONTROLLER (1) Reception in EndPoint0, EndPoint6 Same processing is executed without relations in receive mode in EndPoint0, EndPoint6 every time. Figure 6-16. Data Receiving in EndPoint0, EndPoint6 B uffer D irectory R x In dicatio n µ P D 98502 R x In dicatio n R x In dicatio n...
Page 350: Endpoint2, Endpoint4 Receive Assemble Mode
CHAPTER 6 USB CONTROLLER (3) EndPoint2, EndPoint4, assemble mode The processing in EndPoint2, EndPoint4 receive Assemble mode is explained below. Figure 6-18. EndPoint2, EndPoint4 Receive Assemble Mode B uffer D irectory µ P D 98502 R x In dicatio n In this mode USB Controller issues Rx indication after receiving one data segment.
Page 351: R 4120A Receive Processing
CHAPTER 6 USB CONTROLLER 6.6.5 V 4120A receive processing This section explains the processing that the V 4120A must perform when data is being received. Figure 6-20. V 4120A Receive Processing S ets P ool initialization S ets R x P ool (If necessary) A dds B uffer Directory to P ool Receives the data...
Page 352: Usb Controller Receive Processing
CHAPTER 6 USB CONTROLLER 6.6.6 USB controller receive processing This section presents all of the processing performed by USB Controller at data receiving. 6.6.6.1 Normal mode The following figure illustrates the receive operations performed by USB Controller in Normal Mode. Figure 6-21.
Page 353 CHAPTER 6 USB CONTROLLER Numbers (1) to (9) do not indicate the order in which USB Controller must perform processing. Instead, these numbers correspond to those in the following explanation. USB Controller is in the status where it waits to receive data (USB Packets) from the USB. USB Controller receives data (USB Packets) from the USB.
Page 354: Usb Controller Receive Operations (Assemble Mode)
CHAPTER 6 USB CONTROLLER 6.6.6.2 Assemble mode The following figure illustrates the receive operations performed by USB Controller in Assemble Mode. Figure 6-22. USB Controller Receive Operations (Assemble Mode) W aits data R eceives data from U SB - C R C ve rify - Bit S tuffing verify - N R ZI d ecode S tores the data from U S B to...
Page 355 CHAPTER 6 USB CONTROLLER Numbers (1) to (11) do not indicate the order in which USB Controller must perform processing. Instead, these numbers correspond to those in the following explanation. USB Controller is in the status where it waits to receive data (USB Packets) from the USB. USB Controller receives data (USB Packets) from the USB.
Page 356: Usb Controller Receive Operation Sequence (Separate Mode)
CHAPTER 6 USB CONTROLLER 6.6.6.3 Separate mode The following figure illustrates the receive operations performed by USB Controller in Separate Mode. Figure 6-23. USB Controller Receive Operation Sequence (Separate Mode) W aits data R eceives data from U SB - C R C ve rify - Bit S tuffing verify - N R ZI de code S tores the data from U S B to...
Page 357 CHAPTER 6 USB CONTROLLER Numbers (1) to (12) do not indicate the order in which USB Controller must perform processing. Instead, these numbers correspond to those in the following explanation. USB Controller is in the status where it waits to receive data (USB Packets) from the USB. USB Controller receives data (USB Packets) from the USB.
Page 358: Detection Of Errors On Usb
CHAPTER 6 USB CONTROLLER 6.6.7 Detection of errors on USB USB Controller has some functions which detect some errors on the USB. Errors shown in figure below are related to Isochronous EndPoint and SOF packet. Figure 6-24. USB Timing Errors Correct ISO.
Page 359 CHAPTER 6 USB CONTROLLER data to USB and will set EP1ND bit (Bit 2) in USB General Status Register 2. • Extra Token on EndPoint1: If IN TOKEN packet for EndPoint2 comes which between two SOFs, USB Controller will set EP1ET bit (Bit 3) in USB General Status Register 2.
Page 360: Rx Data Corruption On Isochronous Endpoint
CHAPTER 6 USB CONTROLLER 6.6.8 Rx data corruption on Isochronous EndPoint On Isochronous Rx EndPoint (EP2), one data packet comes per one frame. If any Isochronous data packet doesn’t come between two SOF packet, it is assumed that Isochronous data is corrupted.
Page 361: Rx Fifo Overrun
CHAPTER 6 USB CONTROLLER Figure 6-25. Example of Buffers Including Corrupted Data V alid D ata B uffer D irectory Buffer descriptor V alid Buffer descriptor C orrupted M ax Pack et Size D ata V alid Buffer descriptor Link pointer V alid D ata C orrupted...
Page 362: Rx Indication
CHAPTER 6 USB CONTROLLER (b) Rx assemble mode USB Controller sets EP2FO (EndPoint2 No Data) bit (Bit 9) in USB General Status Register 2. USB Controller writes dummy data to Data Buffer (In fact, USB Controller only increment pointer which addresses Data Buffer by Max Packet Size.
Page 363 CHAPTER 6 USB CONTROLLER When set to a ‘1’, indicates that a buffer overrun occurred. This bit is set only when receiving the data from the EndPoint1. Bit21: Reserved. Bit20: When set to a ‘0’, indicates that a CRC error has not occurred. When set to a ‘1’, indicates that a CRC error has occurred.
Page 364: Power Management
CHAPTER 6 USB CONTROLLER 6.7 Power Management USB Controller has a built in feature that allows it to use interrupts to inform the V 4120A of its having received Suspend or Resume signaling from a Host PC. When the V 4120A receives a Suspend or a Resume, it must perform the appropriate processing.
Page 365: Resume
CHAPTER 6 USB CONTROLLER The V 4120A is not permitted to write to other than USB Controller's USB General Mode Register and USB Interrupt Mask Register 2 while USB Controller is in the Suspend status. Otherwise, after USB Controller enters the Resume status, its operation will be unpredictable.
Page 366: Remote Wake Up
CHAPTER 6 USB CONTROLLER 6.7.3 Remote wake up The Remote Wake Up sequence is shown below. Figure 6-29. Remote Wake Up Sequence H ost P C U S B 4120A C ontroller R eceives the data from other block Sets R R bit (Bit0) in U SB G eneral M ode R egister Starts K-state...
Page 367: Receiving Sof Packet
CHAPTER 6 USB CONTROLLER 6.8 Receiving SOF Packet USB Controller can receive SOF Packets, and check if Frame Number is incremented correctly. In addition, USB Controller can detect the timing skew of SOF Packet. 6.8.1 Receiving SOF Packet and updating the Frame Number After USB Controller receives a SOF Packet, FN field in USB Frame Number/Version Register (Address: 1000_1004H) is updated.
Page 368: Loopback Mode
CHAPTER 6 USB CONTROLLER 6.9 Loopback Mode USB Controller features a built-in loopback function for test purposes. To enable the loopback function, set the LE bit (Bit 1) of the USB General Mode Register to 1. Once the loopback function has been activated, USB Controller gets the data from system memory and places it into the Tx FIFO.
Page 369: Example Of Connection
CHAPTER 6 USB CONTROLLER 6.10 Example of Connection USB Controller is connected to the µ PD98502 internal USB I/O buffer as shown in the following Figure 6-32. Figure 6-32. Example of Connection U S B C ontroller +3.3 V B uffer Ω...
Page 370: Chapter 7 Pci Controller
CHAPTER 7 PCI CONTROLLER 7.1 Overview The PCI Controller supports both NIC mode and Host mode. With the NIC mode, the PCI Controller does not issue configuration cycle and the arbitration function is not enabled. With the Host mode, the PCI Controller can issue configuration cycle and the arbitration function is enabled.
Page 371: Bus Bridge Functions
CHAPTER 7 PCI CONTROLLER 7.2 Bus Bridge Functions 7.2.1 Internal bus to PCI transaction 7.2.1.1 Window size The PCI Controller can have a 2-MB length access window in internal memory space. The V 4120A can access external PCI devices through the access window. The access window can be positioned in the memory range from 1020_0000H to 103F_FFFFH.
Page 372: Posted Write Transaction From Internal Bus To Pci
CHAPTER 7 PCI CONTROLLER 7.2.1.3 Write issue from internal bus to PCI (1) Posted write transaction If IPWRD bit in P_BCNT register is ‘0’, the PCI Controller uses “Posted Write Transaction” rule for write transactions from the internal bus-side to PCI-side. The rule is as follows; Note <1>...
Page 373: Non Posted Write Transaction From Internal Bus To Pci
CHAPTER 7 PCI CONTROLLER (2) Non posted write transaction If IPWRD bit in P_BCNT register is ‘1’, the PCI Controller uses “Non Posted Write Transaction” rule for write transactions from Internal bus-side to PCI-side. In this mode, burst transfers are disconnected at every single word. The rule is as follows;...
Page 374: Delayed Read Transaction From Internal Bus To Pci
CHAPTER 7 PCI CONTROLLER 7.2.1.4 Read issue from internal bus to PCI (1) Delayed read transaction When IDRTD bit in P_BCNT register is ‘0’, the PCI Controller uses “Delayed Read Transaction” rule for read transactions from internal bus-side to PCI-side. The rule is as follows; <1>...
Page 375: Non Delayed Read Transaction From Internal Bus To Pci
CHAPTER 7 PCI CONTROLLER (2) Non delayed read transaction When IDRTD bit in P_BCNT register is ‘1’, the PCI Controller uses “Non Delayed Read Transaction” rule for read transactions from Internal bus-side to PCI-side. In this mode, burst transfers are disconnected at every single word. The rule is as follows;...
Page 376: Pci To Internal Bus Transaction
CHAPTER 7 PCI CONTROLLER 7.2.2 PCI to internal bus transaction 7.2.2.1 Window size The PCI Controller supports a 2-MB address space as the access window from PCI-side to Internal bus-side in PCI memory space. The base address for the window is written to Window Memory Base Address register in configuration space by an external PCI-Host device in NIC mode.
Page 377: Posted Write Transaction From Pci To Internal Bus
CHAPTER 7 PCI CONTROLLER 7.2.2.3 Write issue from PCI to Internal bus (1) Posted write transaction If PPWRD bit in P_BCNT register is ‘0’, the PCI Controller uses “Posted Write Transaction” rule for write transactions from Internal bus-side to PCI-side. The rule is as follows; <1>...
Page 378: Non Posted Write Transaction From Pci To Internal Bus
CHAPTER 7 PCI CONTROLLER (2) Non posted write transaction When PPWRD bit in P_BCNT register is ‘1’, the PCI Controller uses “Non Posted Write Transaction” rule for write transactions from Internal bus-side to PCI-side. In this mode, burst transfers are disconnected at every single word. The rule is as follows;...
Page 379: Delayed Read Transaction From Pci To Internal Bus
CHAPTER 7 PCI CONTROLLER 7.2.2.4 Read issue from PCI to internal bus (1) Delayed read transaction When PDRTD bit in P_BCNT register is ‘0’, the PCI Controller uses “Delayed Read Transaction” rule for read transactions from Internal bus-side to PCI-side. The rule is as follows; <1>...
Page 380: Non Delayed Read Transaction From Pci To Internal Bus
CHAPTER 7 PCI CONTROLLER (2) Non delayed read transaction When PDRTD bit in P_BCNT register is ‘1’, the PCI Controller uses “Non Delayed Read Transaction” rule for read transactions from Internal bus-side to PCI-side. In this mode, burst transfers are disconnected at every single word. The rule is as follows;...
Page 381: Abnormal Termination
CHAPTER 7 PCI CONTROLLER 7.2.3 Abnormal Termination 7.2.3.1 On PCI bus (1) Detecting parity error When the access to the PCI Controller is issued on PCI bus and the PCI Controller detects the address parity error as a target, the PCI Controller issues a target abort to terminate the access. At the same time, the PCI Controller sets “Detected Parity Error”...
Page 382: Warning For Deadlocks
CHAPTER 7 PCI CONTROLLER In the case that the value except for ‘0’ is set to P_RTMR register, the PCI Controller abandons the access when the number of target retry which the PCI Controller is received for the same access goes over the value in P_RTMR register.
Page 383: Pci Power Management Interface
CHAPTER 7 PCI CONTROLLER 7.3 PCI Power Management Interface The PCI Controller has the mechanism for power management compliant to PCI Power Management Interface (PPMI) Rev.1.1 as a PCI-device. The PCI Controller does not control the power state of the chip, but issues signals of power transition from the V 4120A to an external PCI-Host device, or from the PCI-Host device to the V 4120A.
Page 384: Power State Transition
CHAPTER 7 PCI CONTROLLER 7.3.4 Power state transition 7.3.4.1 Transition by issue from PCI-Host An example of the transition sequence is as follows: 1. When PCI-Host wants to change the power state of the chip, it writes the state code to Power State field in PMCSR register.
Page 385: The Sequence Of The Transition By Pme
CHAPTER 7 PCI CONTROLLER 7.3.4.2 Transition by power management event The sequence is as follows: 1. When Power Management Event occurs, the V 4120A writes a ‘1’ to PMERQ bit in P_PPCR register. 2. The PCI Controller asserts PME_B if PME_En bit in PMCSR register is enabled. 3.
Page 386: Functions In Host-Mode
CHAPTER 7 PCI CONTROLLER 7.4 Functions in Host-mode The functions described in this section are available when PMODE is set to low. 7.4.1 Generating configuration cycle 7.4.1.1 How to generate Configuration Cycle The PCI Controller can generates Configuration Cycle on PCI bus by accessing of the following two registers; PCI Configuration Address Register (P_PCAR) PCI Configuration Data Register (P_PCDR) At first, the information like address to be accessed for Configuration Cycle has to be set to P_PCAR register.
Page 387: Device Number Decode Table
CHAPTER 7 PCI CONTROLLER 7.4.1.3 PCI Configuration Data Register (P_PCDR) When bit31 in the PCAR register is set to ‘1’, access to PCDR register generates Configuration Cycle. Read access to P_PCDR register generates Configuration Read Cycle on PCI bus. Write access to P_PCDR register, also, generates Configuration Write Cycle on PCI bus.
Page 388: Pci Bus Arbiter
CHAPTER 7 PCI CONTROLLER Figure 7-14. An Example How to Connect AD [31:16] Signal Line to IDSEL Port A D [x] ID S E L A D [31 :0 ] P C I de vice Figure 7-15. Address Stepping for IDSEL C lock FR A M E # A ddress...
Page 389: Reset Output
CHAPTER 7 PCI CONTROLLER Figure 7-16. Arbitration in Alternating Mode G N T #0 G N T #1 P C I A lterna ting R ota tin g C ontrolle r G N T #3 G N T #2 7.4.2.2 Rotating mode Priority rotates among all PCI master devices including the PCI Controller in this mode.
Page 390: Registers
CHAPTER 7 PCI CONTROLLER 7.5 Registers 7.5.1 Register map Offset Address Register Name Access Description Internal 1000_4000H P_PLBA W/H/B PCI Lower Base Address Register 1000_4004H Reserved 1000_4008H P_IBBA W/H/B Internal Bus Base Address Register 1000_400CH Reserved 1000_4010H P_VERR W/H/B Version Register 1000_4014H P_PCAR W/H/B...
Page 391: P_Plba (Pci Lower Base Address Register)
CHAPTER 7 PCI CONTROLLER 7.5.2 P_PLBA (PCI Lower Base Address Register) When the PCI Controller issues 32-bit PCI address, this register contains PCI base address. When the access from Internal bus-side to PCI-side comes, the PCI Controller replaces the upper 10 bits of the address on internal bus with the upper 10 bits of this register, and issues as the address on PCI bus.
Page 392: P_Pcar (Pci Configuration Address Register)
CHAPTER 7 PCI CONTROLLER 7.5.5 P_PCAR (PCI Configuration Address Register) PCAR register is used to set the information for Configuration Cycle. How to generate Configuration Cycle is described in 7.4.1 Generating configuration cycle. The PCI Controller can executes Configuration Cycle only in Host-mode. Bits Field Default...
Page 393: P_Igsr (Internal Bus-Side General Status Register)
CHAPTER 7 PCI CONTROLLER 7.5.7 P_IGSR (Internal Bus-side General Status Register) IGSR register shows the interrupt status of the PCI Controller to the V 4120A. When an event that triggers interruption occurs, the PCI Controller sets a bit in this register corresponds to the event. When the corresponding bit in IIMR is set, the PCI Controller asserts an internal interrupt signal to the V 4120A.
Page 394: P_Iimr (Internal Bus Interrupt Mask Register)
CHAPTER 7 PCI CONTROLLER 7.5.8 P_IIMR (Internal Bus Interrupt Mask Register) IIMR register masks the interruption for each corresponding event. A mask bit, which locates in the same bit position to a corresponding bit in IGSR, controls interruption triggered by the event. When a bit of this register is reset to ‘0’, the corresponding bit of the IGSR is masked.
Page 395: P_Pgsr (Pci-Side General Status Register)
CHAPTER 7 PCI CONTROLLER 7.5.9 P_PGSR (PCI-side General Status Register) PGSR register shows the interrupt status of the PCI Controller to PCI-side (which means PCI-Host). When an event that triggers interruption occurs, the PCI Controller sets a bit in PGSR corresponds to the type of incident. If the interruption is not masked, the PCI Controller interrupts to PCI-Host using the interrupt signal.
Page 396: P_Iimr (Internal Bus Interrupt Mask Register)
CHAPTER 7 PCI CONTROLLER 7.5.10 P_IIMR (Internal Bus Interrupt Mask Register) IIMR register masks the interruption for each corresponding event. A mask bit, which locates in the same bit position to a corresponding bit in IGSR, controls interruption triggered by the event. When a bit of this register is reset to ‘0’, the corresponding bit of the IGSR is masked.
Page 397: P_Pimr (Pci Interrupt Mask Register)
CHAPTER 7 PCI CONTROLLER 7.5.11 P_PIMR (PCI Interrupt Mask Register) PIMR register masks interruptions. A mask bit, which locates in the same bit position to a corresponding bit in PGSR, can mask the interruption. When a bit of this register is reset to ‘0’, the corresponding bit of the PGSR is masked.
Page 398: P_Hmcr (Host Mode Control Register)
CHAPTER 7 PCI CONTROLLER 7.5.12 P_HMCR (Host Mode Control Register) This register is used to control the PCI-Host functions. Bits Field Default Description Internal PRSTO Reset Out. PCI reset output as Host. The PCI Controller asserts PRSTO during this bit is ‘1’. 30:1 Reserved Hardwired to ‘0’s.
Page 399: P_Bcnt (Bridge Control Register)
CHAPTER 7 PCI CONTROLLER 7.5.15 P_BCNT (Bridge Control Register) This register is used to control the PCI-internal bus bridge function. Bits Field Default Description Internal INITD Initialize done. The V 4120A should set this bit to ‘1’ after the initialization of the chip.
Page 400: P_Ppcr (Pci Power Control Register)
CHAPTER 7 PCI CONTROLLER 7.5.16 P_PPCR (PCI Power Control Register) This register is used to control the power state for PPMI. See 7.6 Information for Software for further details. Bits Field Default Description Internal PMRDY Power Management Ready. ‘1’ indicates that the transition of power state has been done. When PCI-Host writes to PowerState field of PMCSR register in Configuration Space, this bit is reset to ‘0’.
Page 401: P_Rtmr (Retry Timer Register)
CHAPTER 7 PCI CONTROLLER 7.5.18 P_RTMR (Retry Timer Register) This register is used to set the limitation of the number of retry repetition. ‘0’ disables this function. See 7.2.3.1 (5) Received target retry as PCI-master for further details. Bits Field Default Description Internal...
Page 402 CHAPTER 7 PCI CONTROLLER Offset Address Register Name Size Internal Description (byte) 1000_4100H Vendor ID Vendor ID for NEC = 1033H 1000_4102H Device ID Device Specific ID 1000_4104H Command PCI Command 1000_4106H Status PCI Status 1000_4108H Revision ID Revision ID...
Page 403 CHAPTER 7 PCI CONTROLLER 7.5.19.2 Vendor ID register This register identifies the manufacturer of the device. The identifier for NEC is ‘1033H”. Bits Field Default Description Internal 15:0 Vendor ID 1033H Hardwired to ‘1033H’, which means the Vendor ID of NEC 7.5.19.3 Device ID register...
Page 404 CHAPTER 7 PCI CONTROLLER 7.5.19.4 Command register This register provides coarse control over a device’s ability to generate and respond to PCI cycles. This register is valid in Host-mode. The V 4120A should set the register. Bits Field Default Description Internal 15:10 Reserved...
Page 405 CHAPTER 7 PCI CONTROLLER 7.5.19.5 Status register This register is used to show PCI bus related events status. These bits are set when events related to the status on PCI bus and reset to ‘0’ by writing ‘1’. In Host-mode, any bit in this register is not set even if corresponding events occur. Bits Field Default...
Page 406 CHAPTER 7 PCI CONTROLLER 7.5.19.6 Revision ID register This register specifies a device specific revision identifier. Bits Field Default Description Internal Revision ID Hardwired to ‘01H’ that shows the revision number of the chip. 7.5.19.7 Class code register This register is used to identify the generic function of the device. Bits Field Default...
Page 407 CHAPTER 7 PCI CONTROLLER 7.5.19.10 Header type register This register identifies the layout of the second part of the predefined header and also whether or not the device contains multiple functions. Bits Field Default Description Internal Header Type Hardwired to ‘00H’, because the PCI Controller is a single function device and not a PCI-PCI bridge.
Page 408 CHAPTER 7 PCI CONTROLLER 7.5.19.14 Subsystem ID register This register is used to uniquely identify the expansion board or subsystem where the PCI device resides. Bits Field Default Description Internal 15:0 Subsystem ID The V 4120A should set the identifier to this register. 7.5.19.15 Cap_Ptr register This register is used to show a linked list of new capabilities implemented by The PCI Controller.
Page 409 CHAPTER 7 PCI CONTROLLER 7.5.19.19 Max_Lat register This register specifies how often the device needs to get the PCI bus usage. Bits Field Default Description Internal Max_Lat The value should be set by the V 4120A. 7.5.19.20 Cap_ID register This register indicates what kind of data structure of the capability is pointed to. The value ‘01H’ means that the data structure is for the PCI Power Management.
Page 410 CHAPTER 7 PCI CONTROLLER 7.5.19.23 PMCSR register This register is used to manage the PCI function’s power management state as well as to enable/monitor PME. Bits Field Default Description Internal 15:10 PME_Staus This bit is set when the PCI Controller asserts the PME_B signal independent of the PME_En bit.
Page 411: Information For Software
CHAPTER 7 PCI CONTROLLER 7.6 Information for Software 7.6.1 NIC mode 7.6.1.1 Initialization (1) Initialization by the V 4120A The PCI Controller issues “retry” to all accesses from PCI-side until INITD bit in P_BCNT register is set to ‘1’. Therefore, Initialization of the chip should be done before INITD bit is set to ‘1’. The following sequence shows an example of initialization procedures required for the V 4120A.
Page 412: Host Mode
CHAPTER 7 PCI CONTROLLER - Sets a ‘1’ to PME_En bit in PMCSR register, if needed Then, the PCI-Host device initializes internal registers. - Sets the value of base address in P_IBBA register, if needed - Enables mask bits in P_PIMR register, if needed - Sets Retry Timer register, if needed (3) Error In the case that Error described in 7.2.3 Abnormal Termination occurs, the PCI Controller sets bits in Status...
Page 413 CHAPTER 7 PCI CONTROLLER - Sets a ‘1’ to “Bus Master Enable” bit in command register, if the chip executes transaction as PCI-master - Sets a ‘1’ to “Memory Write and Invalidate Enable” bit in command register, if needed - Sets a ‘1’ to “Parity Error Response” bit in command register, if needed - Sets a ‘1’...
Page 414: Chapter 8 Uart
CHAPTER 8 UART 8.1 Overview UART is a serial interface that conforms to the RS-232C communication standard and is equipped with two one- channel interfaces, one for transmission and one for reception. This unit is functionally compatible with the NS16550D. 8.2 UART Block Diagram R E C E IV E R D A T A...
Page 415: Registers
CHAPTER 8 UART 8.3 Registers This controller uses the NEC NA16550L Mega-Function as its internal UART. This UART is functionally identical to the National Semiconductor NS16550D. Refer to the NEC “User’s Manual. Mega FunctionNA16550L” for more information and programming details.
Page 416: Uartrbr (Uart Receiver Data Buffer Register)
CHAPTER 8 UART 8.3.2 UARTRBR (UART Receiver data Buffer Register) This register holds receive data. It is only accessed when the Divisor Latch Access bit (DLAB) is cleared in the UARTLCR. Bits Field Default Description 31:8 Reserved Hardwired to 0. UDATA UART receive data (read only) when DLAB = 0.
Page 417: Uartdlm (Uart Divisor Latch Msb Register)
CHAPTER 8 UART 8.3.6 UARTDLM (UART Divisor Latch MSB Register) This register is used to set the divisor (division rate) for the baud rate generator. The data in this register and the lower 8-bit data in UARTDLL register are together handled as 16-bit data. Bits Field Default...
Page 418: Uartiir (Uart Interrupt Id Register)
CHAPTER 8 UART 8.3.7 UARTIIR (UART Interrupt ID Register) This register indicates priority levels for interrupts and existence of pending interrupt. From highest to lowest priority, these interrupts are receive line status, receive data ready, character timeout, transmit holding register empty, and modem status.
Page 419: Uartfcr (Uart Fifo Control Register)
CHAPTER 8 UART 8.3.8 UARTFCR (UART FIFO Control Register) This register is used to control the FIFOs: enable FIFO, clear FIFO, and set the receive FIFO trigger level. Bits Field Default Description 31:8 Reserved Hardwired to 0. URFTR UART Receive FIFO Trigger level. When the trigger level is reached, a Receive-buffer-Full interrupt is generated, if enable by the ERBFI bit in the UARTIER.
Page 420: Uartlcr (Uart Line Control Register)
CHAPTER 8 UART 8.3.9 UARTLCR (UART Line Control Register) This register is used to specify the format for asynchronous communication and exchange and to set the divisor latch access bit. Bit 6 is used to send the break status to the receive side’s UART. When bit 6 = 1, the serial output (URSDO) is forcibly set to the spacing (0) state.
Page 421: Uartmcr (Uart Modem Control Register)
Hardwired to 0. LOOP Loop-Back Test. 1 = loop-back. 0 = normal operation. This is an NEC internal test function. OUT2 Out 2 (internal signal). 1 = OUT2_B (internal) state active. 0 = OUT2_B (internal) state inactive (reset value). This is a user-defined bit that has no associated external signal. Software can write to the bit, but this has no effect.
Page 422: Uartlsr (Uart Line Status Register)
CHAPTER 8 UART 8.3.11 UARTLSR (UART Line Status Register) This register reports the current state of the transmitter and receiver logic. Bits Field Default Description 31:8 Reserved Hardwired to 0. RFERR Receiver FIFO Error. 1 = parity, framing, or break error in receiver buffer. 0 = no such error.
Page 423: Uartmsr (Uart Modem Status Register)
CHAPTER 8 UART 8.3.12 UARTMSR (UART Modem Status Register) This register reports the current state of and changes in various control signals. Bits Field Default Description 31:8 Reserved Hardwired to 0. Data Carrier Detect. 1 =URDCD_B state active. 0 = URDCD_B state inactive. This bit is the complement of the URDCD_B input signal.
Page 424: Chapter 9 Timer
CHAPTER 9 TIMER 9.1 Overview There are two Timers. The timers are clocked at the system clock rate. All two timers are read/writeable by the CPU. Timers can be read by the CPU while they are counting. They can be automatically reloaded with the “Timer Set Count Register”...
Page 425: Registers
CHAPTER 9 TIMER 9.3 Registers 9.3.1 Register map Offset Address Register Name Access Description 1000_00B0H TMMR W/H/B Timer Mode Register 1000_00B4H TM0CSR W/H/B Timer CH0 Count Set Register 1000_00B8H TM1CSR W/H/B Timer CH1 Count Set Register 1000_00BCH TM0CCR W/H/B Timer CH0 Current Count Register 1000_00C0H TM1CCR W/H/B...
Page 426: Tm0Csr (Timer Ch0 Count Set Register)
CHAPTER 9 TIMER 9.3.3 TM0CSR (Timer CH0 Count Set Register) The Timer CH0 Count Set Register “TM0CSR” is a read-write and 32-bit word-aligned register. CPU (V 4120A) loads a value in it and the counter starts counting down from the (TM0CSR –1) value. When it reaches 0000_0000H, it generates an interrupt to the CPU via Interrupt Status Register “ISR”...
Page 427: Chapter 10 Micro Wire
CHAPTER 10 MICRO WIRE 10.1 Overview This EEPROM interface is compatible with the Micro Wire serial interface. Connection to the “NM93C46” serial EEPROM, manufactured by National Semiconductor, is recommended. Serial EEPROM memory area is accessed in-directly throghout Micro Wire-macro registers, that is ECCR and ERDR registers.
Page 428: Operations
CHAPTER 10 MICRO WIRE 10.2 Operations 10.2.1 Data read at the power up load After reset release, power up load processes starts. In case of the value from EEPROM address 00H is: 1. A5A5H System Controller sets the EEPROM data (address: 01H to 06H) in the internal registers (MACAR1, MACAR2, MACAR3).
Page 429: Registers
CHAPTER 10 MICRO WIRE 10.3 Registers 10.3.1 Register map Offset Address Register Name Access Description 1000_00D0H ECCR W/H/B EEPROM Command Control Register 1000_00D4H ERDR W/H/B EEPROM Read Data Register 1000_00D8H MACAR1 W/H/B MAC Address Register 1 1000_00DCH MACAR2 W/H/B MAC Address Register 2 1000_00E0H MACAR3 W/H/B...
Page 430: Macar3 (Mac Address Register 3)
CHAPTER 10 MICRO WIRE 10.3.6 MACAR3 (MAC Address Register 3) Bits Field Default Description 31:16 SERIAL Stored Serial EEPROM data of address 05H, 06H. EEPROM 06H ADDRESS 15:0 SERIAL EEPROM 05H ADDRESS Preliminary User’s Manual S15543EJ1V0UM...
Page 431: Appendix A Mips Iii Instruction Set Details
APPENDIX A MIPS III INSTRUCTION SET DETAILS This chapter provides a detailed description of the operation of each instruction in both 32- and 64-bit modes. The instructions are listed in alphabetical order. A.1 Instruction Notation Conventions In this chapter, all variable subfields in an instruction format (such as rs , rt , immediate , etc.) are shown in lowercase names.
Page 432: A-1 Cpu Instruction Operation Notations
APPENDIX A MIPS III INSTRUCTION SET DETAILS Table A-1. CPU Instruction Operation Notations Symbol Description ← Assignment Bit string concatenation Replication of bit value x into a y -bit string. x is always a single-bit value Selection of bits y through z of bit string x . Little-endian bit notation is always used. If y is less than z , this xy:z expression is an empty (zero length) bit string 2’s complement or floating-point addition...
Page 433: Load And Store Instructions
APPENDIX A MIPS III INSTRUCTION SET DETAILS (1) Instruction notation examples The following examples illustrate the application of some of the instruction notation conventions: Example 1: GPR [rt] ← immediate || 0 Sixteen zero bits are concatenated with an immediate value (typically 16 bits), and the 32-bit string is assigned to general register rt .
Page 434: Jump And Branch Instructions
APPENDIX A MIPS III INSTRUCTION SET DETAILS As shown in Table A-3, the Access Type field indicates the size of the data item to be loaded or stored. Regardless of access type or byte-numbering order (endian), the address specifies the byte that has the smallest byte address in the addressed field.
Page 435: System Control Coprocessor (Cp0) Instructions
APPENDIX A MIPS III INSTRUCTION SET DETAILS A.4 System Control Coprocessor (CP0) Instructions There are some special limitations imposed on operations involving CP0 that is incorporated within the CPU. Although load and store instructions to transfer data to/from coprocessors and to move control to/from coprocessor instructions are generally permitted by the MIPS architecture, CP0 is given a somewhat protected status since it has responsibility for exception handling and memory management.
Page 436 APPENDIX A MIPS III INSTRUCTION SET DETAILS 26 25 21 20 16 15 11 10 SPECIAL 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 Format: ADD rd, rs, rt Description: The contents of general register rs and the contents of general register rt are added to form the result. The result is placed into general register rd .
Page 437 APPENDIX A MIPS III INSTRUCTION SET DETAILS ADDI ADDI Add Immediate 26 25 21 20 16 15 ADDI immediate 0 0 1 0 0 0 Format: ADDI rt, rs, immediate Description: The 16-bit immediate is sign-extended and added to the contents of general register rs to form the result. The result is placed into general register rt.
Page 438 APPENDIX A MIPS III INSTRUCTION SET DETAILS ADDIU ADDIU Add Immediate Unsigned 26 25 21 20 16 15 ADDIU immediate 0 0 1 0 0 1 Format: ADDIU rt, rs, immediate Description: The 16-bit immediate is sign-extended and added to the contents of general register rs to form the result. The result is placed into general register rt.
Page 439 APPENDIX A MIPS III INSTRUCTION SET DETAILS ADDU ADDU Add Unsigned 26 25 21 20 16 15 11 10 SPECIAL ADDU 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 Format: ADDU rd, rs, rt Description: The contents of general register rs and the contents of general register rt are added to form the result.
Page 440 APPENDIX A MIPS III INSTRUCTION SET DETAILS 26 25 21 20 16 15 11 10 SPECIAL 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 Format: AND rd, rs, rt Description: The contents of general register rs are combined with the contents of general register rt in a bit-wise logical AND operation.
Page 441 APPENDIX A MIPS III INSTRUCTION SET DETAILS ANDI ANDI And Immediate 26 25 21 20 16 15 ANDI immediate 0 0 1 1 0 0 Format: ANDI rt, rs, immediate Description: The 16-bit immediate is zero-extended and combined with the contents of general register rs in a bit-wise logical AND operation.
Page 442 APPENDIX A MIPS III INSTRUCTION SET DETAILS BC0F BC0F Branch On Coprocessor 0 False 26 25 21 20 16 15 COPz offset Note 0 1 0 0 0 0 0 0 0 0 0 1 0 0 X X Format: BC0F offset Description: A branch target address is computed from the sum of the address of the instruction in the delay slot and the 16-bit...
Page 443 APPENDIX A MIPS III INSTRUCTION SET DETAILS BC0FL BC0FL Branch On Coprocessor 0 False Likely (1/2) 26 25 21 20 16 15 COPz BCFL offset Note 0 1 0 0 0 0 0 0 1 0 0 1 0 0 X X Format: BC0FL offset Description:...
Page 444 APPENDIX A MIPS III INSTRUCTION SET DETAILS BC0FL BC0FL Branch On Coprocessor 0 False Likely (2/2) Opcode Table: BC0FL Opcode Coprocessor BC sub-opcode Branch condition number Preliminary User’s Manual S15543EJ1V0UM...
Page 445 APPENDIX A MIPS III INSTRUCTION SET DETAILS BC0T BC0T Branch On Coprocessor 0 True 26 25 21 20 16 15 COPz offset Note 0 1 0 0 0 0 0 0 0 1 0 1 0 0 X X Format: BC0T offset Description: A branch target address is computed from the sum of the address of the instruction in the delay slot and the 16-bit...
Page 446 APPENDIX A MIPS III INSTRUCTION SET DETAILS BC0TL BC0TL Branch On Coprocessor 0 True Likely (1/2) 26 25 21 20 16 15 COPz BCTL offset Note 0 1 0 0 0 0 0 0 1 1 0 1 0 0 X X Format: BC0TL offset Description:...
Page 447 APPENDIX A MIPS III INSTRUCTION SET DETAILS BC0TL BC0TL Branch On Coprocessor 0 True Likely (2/2) Opcode Table: BC0TL Opcode Coprocessor BC sub-opcode Branch condition number Preliminary User’s Manual S15543EJ1V0UM...
Page 448 APPENDIX A MIPS III INSTRUCTION SET DETAILS Branch On Equal 26 25 21 20 16 15 offset 0 0 0 1 0 0 Format: BEQ rs, rt, offset Description: A branch target address is computed from the sum of the address of the instruction in the delay slot and the 16-bit offset , shifted left two bits and sign-extended.
Page 449 APPENDIX A MIPS III INSTRUCTION SET DETAILS BEQL BEQL Branch On Equal Likely 26 25 21 20 16 15 BEQL offset 0 1 0 1 0 0 Format: BEQL rs, rt, offset Description: A branch target address is computed from the sum of the address of the instruction in the delay slot and the 16-bit offset, shifted left two bits and sign-extended.
Page 450 APPENDIX A MIPS III INSTRUCTION SET DETAILS BGEZ BGEZ Branch On Greater Than Or Equal To Zero 26 25 21 20 16 15 REGIMM BGEZ offset 0 0 0 0 0 1 0 0 0 0 1 Format: BGEZ rs, offset Description: A branch target address is computed from the sum of the address of the instruction in the delay slot and the 16-bit offset , shifted left two bits and sign-extended.
Page 451 APPENDIX A MIPS III INSTRUCTION SET DETAILS BGEZAL BGEZAL Branch On Greater Than Or Equal To Zero And Link 26 25 21 20 16 15 REGIMM BGEZAL offset 0 0 0 0 0 1 1 0 0 0 1 Format: BGEZAL rs, offset Description: A branch target address is computed from the sum of the address of the instruction in the delay slot and the 16-bit...
Page 452 APPENDIX A MIPS III INSTRUCTION SET DETAILS BGEZALL BGEZALL Branch On Greater Than Or Equal To Zero And Link Likely 26 25 21 20 16 15 REGIMM BGEZALL offset 0 0 0 0 0 1 1 0 0 1 1 Format: BGEZALL rs, offset Description:...
Page 453 APPENDIX A MIPS III INSTRUCTION SET DETAILS BGEZL BGEZL Branch On Greater Than Or Equal To Zero Likely 26 25 21 20 16 15 REGIMM BGEZL offset 0 0 0 0 0 1 0 0 0 1 1 Format: BGEZL rs, offset Description: A branch target address is computed from the sum of the address of the instruction in the delay slot and the 16-bit offset , shifted left two bits and sign-extended.
Page 454 APPENDIX A MIPS III INSTRUCTION SET DETAILS BGTZ BGTZ Branch On Greater Than Zero 26 25 21 20 16 15 BGTZ offset 0 0 0 1 1 1 0 0 0 0 0 Format: BGTZ rs, offset Description: A branch target address is computed from the sum of the address of the instruction in the delay slot and the 16-bit offset , shifted left two bits and sign-extended.
Page 455 APPENDIX A MIPS III INSTRUCTION SET DETAILS BGTZL BGTZL Branch On Greater Than Zero Likely 26 25 21 20 16 15 BGTZL offset 0 1 0 1 1 1 0 0 0 0 0 Format: BGTZL rs, offset Description: A branch target address is computed from the sum of the address of the instruction in the delay slot and the 16-bit offset , shifted left two bits and sign-extended.
Page 456 APPENDIX A MIPS III INSTRUCTION SET DETAILS BLEZ BLEZ Branch On Less Than Or Equal To Zero 26 25 21 20 16 15 BLEZ offset 0 0 0 1 1 0 0 0 0 0 0 Format: BLEZ rs, offset Description: A branch target address is computed from the sum of the address of the instruction in the delay slot and the 16-bit offset , shifted left two bits and sign-extended.
Page 457 APPENDIX A MIPS III INSTRUCTION SET DETAILS BLEZL BLEZL Branch On Less Than Or Equal To Zero Likely 26 25 21 20 16 15 BLEZL offset 0 1 0 1 1 0 0 0 0 0 0 Format: BLEZL rs, offset Description: A branch target address is computed from the sum of the address of the instruction in the delay slot and the 16-bit offset , shifted left two bits and sign-extended.
Page 458 APPENDIX A MIPS III INSTRUCTION SET DETAILS BLTZ BLTZ Branch On Less Than Zero 26 25 21 20 16 15 REGIMM BLTZ offset 0 0 0 0 0 1 0 0 0 0 0 Format: BLTZ rs, offset Description: A branch target address is computed from the sum of the address of the instruction in the delay slot and the 16-bit offset , shifted left two bits and sign-extended.
Page 459 APPENDIX A MIPS III INSTRUCTION SET DETAILS BLTZAL BLTZAL Branch On Less Than Zero And Link 26 25 21 20 16 15 REGIMM BLTZAL offset 0 0 0 0 0 1 1 0 0 0 0 Format: BLTZAL rs, offset Description: A branch target address is computed from the sum of the address of the instruction in the delay slot and the 16-bit offset, shifted left two bits and sign-extended.
Page 460 APPENDIX A MIPS III INSTRUCTION SET DETAILS BLTZALL BLTZALL Branch On Less Than Zero And Link Likely 26 25 21 20 16 15 REGIMM BLTZALL offset 0 0 0 0 0 1 1 0 0 1 0 Format: BLTZALL rs, offset Description: A branch target address is computed from the sum of the address of the instruction in the delay slot and the 16-bit offset, shifted left two bits and sign-extended.
Page 461 APPENDIX A MIPS III INSTRUCTION SET DETAILS BLTZL BLTZL Branch On Less Than Zero Likely 26 25 21 20 16 15 REGIMM BLTZL offset 0 0 0 0 0 1 0 0 0 1 0 Format: BLTZ rs, offset Description: A branch target address is computed from the sum of the address of the instruction in the delay slot and the 16-bit offset , shifted left two bits and sign-extended.
Page 462 APPENDIX A MIPS III INSTRUCTION SET DETAILS Branch On Not Equal 26 25 21 20 16 15 offset 0 0 0 1 0 1 Format: BNE rs, rt, offset Description: A branch target address is computed from the sum of the address of the instruction in the delay slot and the 16-bit offset, shifted left two bits and sign-extended.
Page 463 APPENDIX A MIPS III INSTRUCTION SET DETAILS BNEL BNEL Branch On Not Equal Likely 26 25 21 20 16 15 BNEL offset 0 1 0 1 0 1 Format: BNEL rs, rt, offset Description: A branch target address is computed from the sum of the address of the instruction in the delay slot and the 16-bit offset, shifted left two bits and sign-extended.
Page 464 APPENDIX A MIPS III INSTRUCTION SET DETAILS BREAK BREAK Breakpoint 26 25 SPECIAL BREAK code 0 0 0 0 0 0 0 0 1 1 0 1 Format: BREAK Description: A breakpoint trap occurs, immediately and unconditionally transferring control to the exception handler. The code field is available for use as software parameters, but is retrieved by the exception handler only by loading the contents of the memory word containing the instruction.
Page 465 APPENDIX A MIPS III INSTRUCTION SET DETAILS CACHE CACHE Cache (1/4) 26 25 21 20 16 15 CACHE base offset 1 0 1 1 1 1 Format: CACHE op, offset (base) Description: The 16-bit offset is sign-extended and added to the contents of general register base to form a virtual address. The virtual address is translated to a physical address using the TLB, and the 5-bit sub-opcode specifies a cache operation for that address.
Page 466 APPENDIX A MIPS III INSTRUCTION SET DETAILS CACHE CACHE Cache (2/4) Write back from a cache goes to main memory. The main memory address to be written is specified by the cache tag and not the physical address translated using TLB.
Page 467 APPENDIX A MIPS III INSTRUCTION SET DETAILS CACHE CACHE Cache (3/4) Code Cache Name Operation Index_Invalidate Set the cache state of the cache block to Invalid. Index_Write_ Examine the cache state and W bit of the primary data cache block at the index Back_Invalidate specified by the virtual address.
Page 468 APPENDIX A MIPS III INSTRUCTION SET DETAILS CACHE CACHE Cache (4/4) Operation: vAddr ← ((offset 32, 64 T: || offset ) + GPR [base] 15...0 (pAddr, uncached) ← AddressTranslation (vAddr, DATA) CacheOp (op, vAddr, pAddr) Exceptions: Coprocessor unusable exception TLB Refill exception TLB Invalid exception Bus Error exception Address Error exception...
Page 469 APPENDIX A MIPS III INSTRUCTION SET DETAILS DADD DADD Doubleword Add 26 25 21 20 16 15 11 10 SPECIAL DADD 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 0 0 Format: DADD rd, rs, rt Description: The contents of general register rs and the contents of general register rt are added to form the result.
Page 470 APPENDIX A MIPS III INSTRUCTION SET DETAILS DADDI DADDI Doubleword Add Immediate 26 25 21 20 16 15 DADDI immediate 0 1 1 0 0 0 Format: DADDI rt, rs, immediate Description: The 16-bit immediate is sign-extended and added to the contents of general register rs to form the result. The result is placed into general register rt.
Page 471 APPENDIX A MIPS III INSTRUCTION SET DETAILS DADDIU DADDIU Doubleword Add Immediate Unsigned 26 25 21 20 16 15 DADDIU immediate 0 1 1 0 0 1 Format: DADDIU rt, rs, immediate Description: The 16-bit immediate is sign-extended and added to the contents of general register rs to form the result. The result is placed into general register rt.
Page 472 APPENDIX A MIPS III INSTRUCTION SET DETAILS DADDU DADDU Doubleword Add Unsigned 26 25 21 20 16 15 11 10 SPECIAL DADDU 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 0 1 Format: DADDU rd, rs, rt Description: The contents of general register rs and the contents of general register rt are added to form the result.
Page 473 APPENDIX A MIPS III INSTRUCTION SET DETAILS DDIV DDIV Doubleword Divide 26 25 21 20 16 15 SPECIAL DDIV 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 Format: DDIV rs, rt Description:...
Page 474 APPENDIX A MIPS III INSTRUCTION SET DETAILS DDIVU DDIVU Doubleword Divide Unsigned 26 25 21 20 16 15 SPECIAL DDIVU 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 Format: DDIVU rs, rt Description:...
Page 475 APPENDIX A MIPS III INSTRUCTION SET DETAILS Divide 26 25 21 20 16 15 SPECIAL 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 0 Format: DIV rs, rt Description: The contents of general register rs are divided by the contents of general register rt, treating both operands as 2’s complement values.
Page 476 APPENDIX A MIPS III INSTRUCTION SET DETAILS DIVU DIVU Divide Unsigned 26 25 21 20 16 15 SPECIAL DIVU 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 1 Format: DIVU rs, rt Description:...
Page 477 APPENDIX A MIPS III INSTRUCTION SET DETAILS DMACC DMACC Doubleword Multiply and Accumulate (1/3) 26 25 21 20 16 15 11 10 SPECIAL DMACC 0 0 0 0 0 0 0 0 0 1 0 1 0 0 1 Format: DMACC rd, rs, rt DMACCU rd, rs, rt DMACCS rd, rs, rt...
Page 478 APPENDIX A MIPS III INSTRUCTION SET DETAILS DMACC DMACC Doubleword Multiply and Accumulate (2/3) • When saturation processing is not executed (sat = 0): DMACC, DMACCU instructions The contents of general register rs is multiplied by the contents of general register rt . If both operands are set as "us = 1"...
Page 479 APPENDIX A MIPS III INSTRUCTION SET DETAILS DMACC DMACC Doubleword Multiply and Accumulate (3/3) Operation: 64, sat=0, us=0 (DMACC instruction) temp1 ← ((GPR[rs] || GPR [rs]) * ((GPR[rt] || GPR [rt]) temp2 ← temp1 + LO LO ← temp2 GPR[rd] ← LO 64, sat=0, us=1 (DMACCU instruction) temp1 ←...
Page 480 APPENDIX A MIPS III INSTRUCTION SET DETAILS DMFC0 DMFC0 Doubleword Move From System Control Coprocessor 26 25 21 20 16 15 11 10 COP0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 Format: DMFC0 rt, rd Description:...
Page 481 APPENDIX A MIPS III INSTRUCTION SET DETAILS DMTC0 DMTC0 Doubleword Move To System Control Coprocessor 26 25 21 20 16 15 11 10 COP0 0 1 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 Format: DMTC0 rt, rd Description:...
Page 482 APPENDIX A MIPS III INSTRUCTION SET DETAILS DMULT DMULT Doubleword Multiply 26 25 21 20 16 15 SPECIAL DMULT 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 Format: DMULT rs, rt Description:...
Page 483 APPENDIX A MIPS III INSTRUCTION SET DETAILS DMULTU DMULTU Doubleword Multiply Unsigned 26 25 21 20 16 15 SPECIAL DMULTU 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 1 Format: DMULTU rs, rt Description:...
Page 484 APPENDIX A MIPS III INSTRUCTION SET DETAILS DSLL DSLL Doubleword Shift Left Logical 26 25 21 20 16 15 11 10 SPECIAL DSLL 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 Format: DSLL rd, rt, sa Description:...
Page 485 APPENDIX A MIPS III INSTRUCTION SET DETAILS DSLLV DSLLV Doubleword Shift Left Logical Variable 26 25 21 20 16 15 11 10 SPECIAL DSLLV 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 Format: DSLLV rd, rt, rs Description:...
Page 486 APPENDIX A MIPS III INSTRUCTION SET DETAILS DSLL32 DSLL32 Doubleword Shift Left Logical + 32 26 25 21 20 16 15 11 10 SPECIAL DSLL32 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 Format: DSLL32 rd, rt, sa Description:...
Page 487 APPENDIX A MIPS III INSTRUCTION SET DETAILS DSRA DSRA Doubleword Shift Right Arithmetic 26 25 21 20 16 15 11 10 SPECIAL DSRA 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 1 1 Format: DSRA rd, rt, sa Description:...
Page 488 APPENDIX A MIPS III INSTRUCTION SET DETAILS DSRAV DSRAV Doubleword Shift Right Arithmetic Variable 26 25 21 20 16 15 11 10 SPECIAL DSRAV 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 1 Format: DSRAV rd, rt, rs Description:...
Page 489 APPENDIX A MIPS III INSTRUCTION SET DETAILS DSRA32 DSRA32 Doubleword Shift Right Arithmetic + 32 26 25 21 20 16 15 11 10 SPECIAL DSRA32 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 Format: DSRA32 rd, rt, sa Description:...
Page 490 APPENDIX A MIPS III INSTRUCTION SET DETAILS DSRL DSRL Doubleword Shift Right Logical 26 25 21 20 16 15 11 10 SPECIAL DSRL 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 1 0 Format: DSRL rd, rt, sa Description:...
Page 491 APPENDIX A MIPS III INSTRUCTION SET DETAILS DSRLV DSRLV Doubleword Shift Right Logical Variable 26 25 21 20 16 15 11 10 SPECIAL DSRLV 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 0 Format: DSRLV rd, rt, rs Description:...
Page 492 APPENDIX A MIPS III INSTRUCTION SET DETAILS DSRL32 DSRL32 Doubleword Shift Right Logical + 32 26 25 21 20 16 15 11 10 SPECIAL DSRL32 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 0 Format: DSRL32 rd, rt, sa Description:...
Page 493 APPENDIX A MIPS III INSTRUCTION SET DETAILS DSUB DSUB Doubleword Subtract 26 25 21 20 16 15 11 10 SPECIAL DSUB 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 1 0 Format: DSUB rd, rs, rt Description: The contents of general register rt are subtracted from the contents of general register rs to form a result.
Page 494 APPENDIX A MIPS III INSTRUCTION SET DETAILS DSUBU DSUBU Doubleword Subtract Unsigned 26 25 21 20 16 15 11 10 SPECIAL DSUBU 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 1 1 Format: DSUBU rd, rs, rt Description: The contents of general register rt are subtracted from the contents of general register rs to form a result.
Page 495 APPENDIX A MIPS III INSTRUCTION SET DETAILS ERET ERET Exception Return 26 25 24 COP0 ERET 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 Format: ERET...
Page 496 APPENDIX A MIPS III INSTRUCTION SET DETAILS HIBERNATE HIBERNATE Hibernate 26 25 24 COP0 HIBERNATE 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 1 Format: HIBERNATE...
Page 497 APPENDIX A MIPS III INSTRUCTION SET DETAILS Jump 26 25 target 0 0 0 0 1 0 Format: J target Description: The 26-bit target address is shifted left two bits and combined with the high-order four bits of the address of the delay slot.
Page 498 APPENDIX A MIPS III INSTRUCTION SET DETAILS Jump And Link 26 25 target 0 0 0 0 1 1 Format: JAL target Description: The 26-bit target address is shifted left two bits and combined with the high-order four bits of the address of the delay slot.
Page 499 APPENDIX A MIPS III INSTRUCTION SET DETAILS JALR JALR Jump And Link Register 26 25 21 20 16 15 11 10 SPECIAL JALR 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 Format: JALR rs JALR rd, rs...
Page 500 APPENDIX A MIPS III INSTRUCTION SET DETAILS JALX JALX Jump And Link Exchange 26 25 JALX target 011101 Format: JALX target Description: When a MIPS16 instruction can be executed, a 26-bit target is shifted to left by 2 bits and then added to higher 4 bits of the delay slot's address to make a target address.
Page 501 APPENDIX A MIPS III INSTRUCTION SET DETAILS Jump Register 26 25 21 20 SPECIAL 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 Format: JR rs Description:...
Page 502 APPENDIX A MIPS III INSTRUCTION SET DETAILS Load Byte 26 25 21 20 16 15 base offset 1 0 0 0 0 0 Format: LB rt, offset (base) Description: The 16-bit offset is sign-extended and added to the contents of general register base to form a virtual address. The contents of the byte at the memory location specified by the effective address are sign-extended and loaded into general register rt .
Page 503 APPENDIX A MIPS III INSTRUCTION SET DETAILS Load Byte Unsigned 26 25 21 20 16 15 base offset 1 0 0 1 0 0 Format: LBU rt, offset (base) Description: The 16-bit offset is sign-extended and added to the contents of general register base to form a virtual address. The contents of the byte at the memory location specified by the effective address are zero-extended and loaded into general register rt .
Page 504 APPENDIX A MIPS III INSTRUCTION SET DETAILS Load Doubleword 26 25 21 20 16 15 base offset 1 1 0 1 1 1 Format: LD rt, offset (base) Description: The 16-bit offset is sign-extended and added to the contents of general register base to form a virtual address. The contents of the 64-bit doubleword at the memory location specified by the effective address are loaded into general register rt .
Page 505 APPENDIX A MIPS III INSTRUCTION SET DETAILS Load Doubleword Left (1/3) 26 25 21 20 16 15 base offset 0 1 1 0 1 0 Format: LDL rt, offset (base) Description: This instruction can be used in combination with the LDR instruction to load a register with eight consecutive bytes from memory, when the bytes cross a doubleword boundary.
Page 506 APPENDIX A MIPS III INSTRUCTION SET DETAILS Load Doubleword Left (2/3) The contents of general register rt are internally bypassed within the processor so that no NOP is needed between an immediately preceding load instruction which specifies register rt and a following LDL (or LDR) instruction which also specifies register rt .
Page 507 APPENDIX A MIPS III INSTRUCTION SET DETAILS Load Doubleword Left (3/3) Given a doubleword in a register and a doubleword in memory, the operation of LDL is as follows: Register Memory vAddr2..0 Destination Type Offset (LEM) P B C D E F G H O P C D E F G H N O P D E F G H M N O P E F G H...
Page 508 APPENDIX A MIPS III INSTRUCTION SET DETAILS Load Doubleword Right (1/3) 26 25 21 20 16 15 base offset 0 1 1 0 1 1 Format: LDR rt, offset (base) Description: This instruction can be used in combination with the LDL instruction to load a register with eight consecutive bytes from memory, when the bytes cross a doubleword boundary.
Page 509 APPENDIX A MIPS III INSTRUCTION SET DETAILS Load Doubleword Right (2/3) The contents of general register rt are internally bypassed within the processor so that no NOP is needed between an immediately preceding load instruction which specifies register rt and a following LDR (or LDL) instruction which also specifies register rt .
Page 510 APPENDIX A MIPS III INSTRUCTION SET DETAILS Load Doubleword Right (3/3) Given a doubleword in a register and a doubleword in memory, the operation of LDR is as follows: Register Memory vAddr2..0 Destination Type Offset (LEM) I J K L MN O P A I J K L M N O A B I J K L M N A B C I J K L M...
Page 511 APPENDIX A MIPS III INSTRUCTION SET DETAILS Load Halfword 26 25 21 20 16 15 base offset 1 0 0 0 0 1 Format: LH rt, offset (base) Description: The 16-bit offset is sign-extended and added to the contents of general register base to form a virtual address. The contents of the halfword at the memory location specified by the effective address are sign-extended and loaded into general register rt .
Page 512 APPENDIX A MIPS III INSTRUCTION SET DETAILS Load Halfword Unsigned 26 25 21 20 16 15 base offset 1 0 0 1 0 1 Format: LHU rt, offset (base) Description: The 16-bit offset is sign-extended and added to the contents of general register base to form a virtual address. The contents of the halfword at the memory location specified by the effective address are zero-extended and loaded into general register rt .
Page 513 APPENDIX A MIPS III INSTRUCTION SET DETAILS Load Upper Immediate 26 25 21 20 16 15 immediate 0 0 1 1 1 1 0 0 0 0 0 Format: LUI rt, immediate Description: The 16-bit immediate is shifted left 16 bits and concatenated to 16 bits of zeros. The result is placed into general register rt .
Page 514 APPENDIX A MIPS III INSTRUCTION SET DETAILS Load Word 26 25 21 20 16 15 base offset 1 0 0 0 1 1 Format: LW rt, offset (base) Description: The 16-bit offset is sign-extended and added to the contents of general register base to form a virtual address. The contents of the word at the memory location specified by the effective address are loaded into general register rt .
Page 515 APPENDIX A MIPS III INSTRUCTION SET DETAILS Load Word Left (1/3) 26 25 21 20 16 15 base offset 1 0 0 0 1 0 Format: LWL rt, offset (base) Description: This instruction can be used in combination with the LWR instruction to load a register with four consecutive bytes from memory, when the bytes cross a word boundary.
Page 516 APPENDIX A MIPS III INSTRUCTION SET DETAILS Load Word Left (2/3) The contents of general register rt are internally bypassed within the processor so that no NOP is needed between an immediately preceding load instruction which specifies register rt and a following LWL (or LWR) instruction which also specifies register rt .
Page 517 APPENDIX A MIPS III INSTRUCTION SET DETAILS Load Word Left (3/3) Given a doubleword in a register and a doubleword in memory, the operation of LWL is as follows: Register Memory vAddr2..0 Destination Type Offset (LEM) S S S S P F G H S S S S O P G H S S S S N O P H S S S S MN O P...
Page 518 APPENDIX A MIPS III INSTRUCTION SET DETAILS Load Word Right (1/3) 26 25 21 20 16 15 base offset 1 0 0 1 1 0 Format: LWR rt, offset (base) Description: This instruction can be used in combination with the LWL instruction to load a register with four consecutive bytes from memory, when the bytes cross a word boundary.
Page 519 APPENDIX A MIPS III INSTRUCTION SET DETAILS Load Word Right (2/3) The contents of general register rt are internally bypassed within the processor so that no NOP is needed between an immediately preceding load instruction which specifies register rt and a following LWR (or LWL) instruction which also specifies register rt .
Page 520 APPENDIX A MIPS III INSTRUCTION SET DETAILS Load Word Right (3/3) Given a word in a register and a word in memory, the operation of LWR is as follows: Register Memory vAddr2..0 Destination Type Offset (LEM) S S S S MN O P S S S S E M N O S S S S E F M N S S S S E F GM...
Page 521 APPENDIX A MIPS III INSTRUCTION SET DETAILS Load Word Unsigned 26 25 21 20 16 15 base offset 1 0 1 1 1 1 Format: LWU rt, offset (base) Description: The 16-bit offset is sign-extended and added to the contents of general register base to form a virtual address. The contents of the word at the memory location specified by the effective address are loaded into general register rt .
Page 522 APPENDIX A MIPS III INSTRUCTION SET DETAILS MACC MACC Multiply and Accumulate (1/5) 26 25 21 20 16 15 11 10 SPECIAL MACC 0 0 0 0 0 0 1 0 1 0 0 0 Format: MACC rd, rs, rt MACCU rd, rs, rt MACCHI rd, rs, rt MACCHIU rd, rs, rt...
Page 523 APPENDIX A MIPS III INSTRUCTION SET DETAILS MACC MACC Multiply and Accumulate (2/5) • When saturation processing is not executed (sat = 0): MACC, MACCU, MACCHI, MACCHIU instructions The contents of general register rs is multiplied to the contents of general register rt . If both operands are set as "us = 1"...
Page 524 APPENDIX A MIPS III INSTRUCTION SET DETAILS MACC MACC Multiply and Accumulate (3/5) Operation: 32, sat=0, hi=0, us=0 (MACC instruction) temp1 ← GPR[rs] * GPR[rt] temp2 ← temp1 + (HI || LO) LO ← temp2 63..32 HI ← temp2 31..0 GPR[rd] ←...
Page 525 APPENDIX A MIPS III INSTRUCTION SET DETAILS MACC MACC Multiply and Accumulate (4/5) 32, sat=1, hi=1, us=0 (MACCHIS instruction) temp1 ← GPR[rs] * GPR[rt] temp2 ← saturation(temp1 + (HI || LO)) LO ← temp2 63..32 HI ← temp2 31..0 GPR[rd] ← HI 32, sat=1, hi=1, us=1 (MACCHIUS instruction) temp1 ←...
Page 526 APPENDIX A MIPS III INSTRUCTION SET DETAILS MACC MACC Multiply and Accumulate (5/5) 64, sat=1, hi=0, us=0 (MACCS instruction) temp1 ← ((GPR[rs] || GPR[rs]) * ((GPR[rt] || GPR[rt]) temp2 ← saturation(temp1 + (HI || LO 31..0 31..0 LO ← ((temp2 || temp2 63..32 HI ←...
Page 527 APPENDIX A MIPS III INSTRUCTION SET DETAILS MFC0 MFC0 Move From System Control Coprocessor 26 25 21 20 16 15 11 10 COP0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Format: MFC0 rt, rd Description:...
Page 528 APPENDIX A MIPS III INSTRUCTION SET DETAILS MFHI MFHI Move From HI 26 25 16 15 11 10 SPECIAL MFHI 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 Format: MFHI rd...
Page 529 APPENDIX A MIPS III INSTRUCTION SET DETAILS MFLO MFLO Move From LO 26 25 16 15 11 10 SPECIAL MFLO 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 Format: MFLO rd...
Page 530 APPENDIX A MIPS III INSTRUCTION SET DETAILS MTC0 MTC0 Move To Coprocessor0 26 25 21 20 16 15 11 10 COP0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 Format: MTC0 rt, rd Description:...
Page 531 APPENDIX A MIPS III INSTRUCTION SET DETAILS MTHI MTHI Move To HI 26 25 21 20 SPECIAL MTHI 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 Format: MTHI rs Description:...
Page 532 APPENDIX A MIPS III INSTRUCTION SET DETAILS MTLO MTLO Move To LO 26 25 21 20 SPECIAL MTLO 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 1 Format: MTLO rs Description:...
Page 533 APPENDIX A MIPS III INSTRUCTION SET DETAILS MULT MULT Multiply 26 25 21 20 16 15 SPECIAL MULT 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 Format: MULT rs, rt Description:...
Page 534 APPENDIX A MIPS III INSTRUCTION SET DETAILS MULTU MULTU Multiply Unsigned 26 25 21 20 16 15 SPECIAL MULTU 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 1 Format: MULTU rs, rt Description:...
Page 535 APPENDIX A MIPS III INSTRUCTION SET DETAILS 26 25 21 20 16 15 11 10 SPECIAL 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 1 1 Format: NOR rd, rs, rt Description: The contents of general register rs are combined with the contents of general register rt in a bit-wise logical NOR operation.
Page 536 APPENDIX A MIPS III INSTRUCTION SET DETAILS 26 25 21 20 16 15 11 10 SPECIAL 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 1 Format: OR rd, rs, rt Description: The contents of general register rs are combined with the contents of general register rt in a bit-wise logical OR operation.
Page 537 APPENDIX A MIPS III INSTRUCTION SET DETAILS Or Immediate 26 25 21 20 16 15 immediate 0 0 1 1 0 1 Format: ORI rt, rs, immediate Description: The 16-bit immediate is zero-extended and combined with the contents of general register rs in a bit-wise logical OR operation.
Page 538 APPENDIX A MIPS III INSTRUCTION SET DETAILS Store Byte 26 25 21 20 16 15 base offset 1 0 1 0 0 0 Format: SB rt, offset (base) Description: The 16-bit offset is sign-extended and added to the contents of general register base to form a virtual address. The least-significant byte of register rt is stored at the effective address.
Page 539 APPENDIX A MIPS III INSTRUCTION SET DETAILS Store Doubleword 26 25 21 20 16 15 base offset 1 1 1 1 1 1 Format: SD rt, offset (base) Description: The 16-bit offset is sign-extended and added to the contents of general register base to form a virtual address. The contents of general register rt are stored at the memory location specified by the effective address.
Page 540 APPENDIX A MIPS III INSTRUCTION SET DETAILS Store Doubleword Left (1/3) 26 25 21 20 16 15 base offset 1 0 1 1 0 0 Format: SDL rt, offset (base) Description: This instruction can be used with the SDR instruction to store the contents of a register into eight consecutive bytes of memory, when the bytes cross a doubleword boundary.
Page 541 APPENDIX A MIPS III INSTRUCTION SET DETAILS Store Doubleword Left (2/3) An address error exception is not occurred that specify address is not located in doubleword boundary. This operation is defined in 64-bit mode or in 32-bit kernel mode. Execution of this instruction in 32-bit user or supervisor mode causes a reserved instruction exception.
Page 542 APPENDIX A MIPS III INSTRUCTION SET DETAILS Store Doubleword Left (3/3) Given a doubleword in a register and a doubleword in memory, the operation of SDL instruction is as follows: Register Memory vAddr2..0 Destination Type Offset (LEM) I J K L MN O A I J K L MN A B I J K L M A B C I J K L A B C D...
Page 543 APPENDIX A MIPS III INSTRUCTION SET DETAILS Store Doubleword Right (1/3) 26 25 21 20 16 15 base offset 1 0 1 1 0 1 Format: SDR rt, offset (base) Description: This instruction can be used with the SDL instruction to store the contents of a register into eight consecutive bytes of memory, when the bytes cross a boundary between two doublewords.
Page 544 APPENDIX A MIPS III INSTRUCTION SET DETAILS Store Doubleword Right (2/3) An address error exception is not occurred that specify address is not located in doubleword boundary. This operation is defined in 64-bit mode or in 32-bit kernel mode. Execution of this instruction in 32-bit user or supervisor mode causes a reserved instruction exception.
Page 545 APPENDIX A MIPS III INSTRUCTION SET DETAILS Store Doubleword Right (3/3) Given a doubleword in a register and a doubleword in memory, the operation of SDR instruction is as follows: Register Memory vAddr2..0 Destination Type Offset (LEM) A B C D E F G H B C D E F G H P C D E F G H O P D E F G H N O P...
Page 546 APPENDIX A MIPS III INSTRUCTION SET DETAILS Store Halfword 26 25 21 20 16 15 base offset 1 0 1 0 0 1 Format: SH rt, offset (base) Description: The 16-bit offset is sign-extended and added to the contents of general register base to form an unsigned effective address.
Page 547 APPENDIX A MIPS III INSTRUCTION SET DETAILS Shift Left Logical 26 25 21 20 16 15 11 10 SPECIAL 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Format: SLL rd, rt, sa Description: The contents of general register rt are shifted left by sa bits, inserting zeros into the low-order bits.
Page 548 APPENDIX A MIPS III INSTRUCTION SET DETAILS SLLV SLLV Shift Left Logical Variable 26 25 21 20 16 15 11 10 SPECIAL SLLV 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 Format: SLLV rd, rt, rs Description:...
Page 549 APPENDIX A MIPS III INSTRUCTION SET DETAILS Set On Less Than 26 25 21 20 16 15 11 10 SPECIAL 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 Format: SLT rd, rs, rt Description: The contents of general register rt are subtracted from the contents of general register rs .
Page 550 APPENDIX A MIPS III INSTRUCTION SET DETAILS SLTI SLTI Set On Less Than Immediate 26 25 21 20 16 15 SLTI immediate 0 0 1 0 1 0 Format: SLTI rt, rs, immediate Description: The 16-bit immediate is sign-extended and subtracted from the contents of general register rs. Considering both quantities as signed integers, if rs is less than the sign-extended immediate , the result is set to 1;...
Page 551 APPENDIX A MIPS III INSTRUCTION SET DETAILS SLTIU SLTIU Set On Less Than Immediate Unsigned 26 25 21 20 16 15 SLTIU immediate 0 0 1 0 1 1 Format: SLTIU rt, rs, immediate Description: The 16-bit immediate is sign-extended and subtracted from the contents of general register rs. Considering both quantities as unsigned integers, if rs is less than the sign-extended immediate , the result is set to 1;...
Page 552 APPENDIX A MIPS III INSTRUCTION SET DETAILS SLTU SLTU Set On Less Than Unsigned 26 25 21 20 16 15 11 10 SPECIAL SLTU 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 1 1 Format: SLTU rd, rs, rt Description:...
Page 553 APPENDIX A MIPS III INSTRUCTION SET DETAILS Shift Right Arithmetic 26 25 21 20 16 15 11 10 SPECIAL 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 Format: SRA rd, rt, sa Description: The contents of general register rt are shifted right by sa bits, sign-extending the high-order bits.
Page 554 APPENDIX A MIPS III INSTRUCTION SET DETAILS SRAV SRAV Shift Right Arithmetic Variable 26 25 21 20 16 15 11 10 SPECIAL SRAV 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 Format: SRAV rd, rt, rs Description:...
Page 555 APPENDIX A MIPS III INSTRUCTION SET DETAILS Shift Right Logical 26 25 21 20 16 15 11 10 SPECIAL 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 Format: SRL rd, rt, sa Description: The contents of general register rt are shifted right by sa bits, inserting zeros into the high-order bits.
Page 556 APPENDIX A MIPS III INSTRUCTION SET DETAILS SRLV SRLV Shift Right Logical Variable 26 25 21 20 16 15 11 10 SPECIAL SRLV 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 Format: SRLV rd, rt, rs Description:...
Page 557 APPENDIX A MIPS III INSTRUCTION SET DETAILS STANDBY STANDBY Standby 26 25 COP0 STANDBY 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 Format: STANDBY Description:...
Page 558 APPENDIX A MIPS III INSTRUCTION SET DETAILS Subtract 26 25 21 20 16 15 11 10 SPECIAL 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 Format: SUB rd, rs, rt Description: The contents of general register rt are subtracted from the contents of general register rs to form a result.
Page 559 APPENDIX A MIPS III INSTRUCTION SET DETAILS SUBU SUBU Subtract Unsigned 26 25 21 20 16 15 11 10 SPECIAL SUBU 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 1 Format: SUBU rd, rs, rt Description: The contents of general register rt are subtracted from the contents of general register rs to form a result.
Page 560 APPENDIX A MIPS III INSTRUCTION SET DETAILS SUSPEND SUSPEND Suspend 26 25 COP0 SUSPEND 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 Format: SUSPEND Description:...
Page 561 APPENDIX A MIPS III INSTRUCTION SET DETAILS Store Word 26 25 21 20 16 15 base offset 1 0 1 0 1 1 Format: SW rt, offset (base) Description: The 16-bit offset is sign-extended and added to the contents of general register base to form a virtual address. The contents of general register rt are stored at the memory location specified by the effective address.
Page 562 APPENDIX A MIPS III INSTRUCTION SET DETAILS Store Word Left (1/3) 26 25 21 20 16 15 base offset 1 0 1 0 1 0 Format: SWL rt, offset (base) Description: This instruction can be used with the SWR instruction to store the contents of a register into four consecutive bytes of memory, when the bytes cross a word boundary.
Page 563 APPENDIX A MIPS III INSTRUCTION SET DETAILS Store Word Left (2/3) Operation: vAddr ← ((offset || offset ) + GPR [base] 15...0 (pAddr, uncached) ← AddressTranslation (vAddr, DATA) pAddr ← pAddr || (pAddr xor ReverseEndian PSIZE - 1...3 2...0 if BigEndianMem = 0 then pAddr ←...
Page 564 APPENDIX A MIPS III INSTRUCTION SET DETAILS Store Word Left (3/3) Given a doubleword in a register and a doubleword in memory, the operation of SWL is as follows: Register Memory vAddr2..0 Destination Type Offset (LEM) I J K L MN O E I J K L MN E F I J K L M E F G I J K L E F G H...
Page 565 APPENDIX A MIPS III INSTRUCTION SET DETAILS Store Word Right (1/3) 26 25 21 20 16 15 base offset 1 0 1 1 1 0 Format: SWR rt, offset (base) Description: This instruction can be used with the SWL instruction to store the contents of a register into four consecutive bytes of memory, when the bytes cross a boundary between two words.
Page 566 APPENDIX A MIPS III INSTRUCTION SET DETAILS Store Word Right (2/3) Operation: vAddr ← ((offset || offset ) + GPR [base] 15...0 (pAddr, uncached) ← AddressTranslation (vAddr, DATA) pAddr ← pAddr || (pAddr xor ReverseEndian PSIZE - 1...3 2...0 if BigEndianMem = 1 then pAddr ←...
Page 567 APPENDIX A MIPS III INSTRUCTION SET DETAILS Store Word Right (3/3) Given a doubleword in a register and a doubleword in memory, the operation of SWR instruction is as follows: Register Memory vAddr2.. Destination Type Offset (LEM) I J K L E F G H I J K L F G H P I J K L G H O P I J K L H N O P...
Page 568 APPENDIX A MIPS III INSTRUCTION SET DETAILS SYNC SYNC Synchronize 26 25 SPECIAL SYNC 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 Format: SYNC...
Page 569 APPENDIX A MIPS III INSTRUCTION SET DETAILS SYSCALL SYSCALL System Call 26 25 SPECIAL SYSCALL Code 0 0 0 0 0 0 0 0 1 1 0 0 Format: SYSCALL Description: A system call exception occurs, immediately and unconditionally transferring control to the exception handler. The code field is available for use as software parameters, but is retrieved by the exception handler only by loading the contents of the memory word containing the instruction.
Page 570 APPENDIX A MIPS III INSTRUCTION SET DETAILS Trap If Equal 26 25 21 20 16 15 SPECIAL code 0 0 0 0 0 0 1 1 0 1 0 0 Format: TEQ rs, rt Description: The contents of general register rt are compared to general register rs . If the contents of general register rs are equal to the contents of general register rt , a trap exception occurs.
Page 571 APPENDIX A MIPS III INSTRUCTION SET DETAILS TEQI TEQI Trap If Equal Immediate 26 25 21 20 16 15 REGIMM TEQI immediate 0 0 0 0 0 1 0 1 1 0 0 Format: TEQI rs, immediate Description: The 16-bit immediate is sign-extended and compared to the contents of general register rs . If the contents of general register rs are equal to the sign-extended immediate , a trap exception occurs.
Page 572 APPENDIX A MIPS III INSTRUCTION SET DETAILS Trap If Greater Than Or Equal 26 25 21 20 16 15 SPECIAL code 0 0 0 0 0 0 1 1 0 0 0 0 Format: TGE rs, rt Description: The contents of general register rt are compared to the contents of general register rs . Considering both quantities as signed integers, if the contents of general register rs are greater than or equal to the contents of general register rt , a trap exception occurs.
Page 573 APPENDIX A MIPS III INSTRUCTION SET DETAILS TGEI TGEI Trap If Greater Than Or Equal Immediate 26 25 21 20 16 15 REGIMM TGEI immediate 0 0 0 0 0 1 0 1 0 0 0 Format: TGEI rs, immediate Description: The 16-bit immediate is sign-extended and compared to the contents of general register rs .
Page 574 APPENDIX A MIPS III INSTRUCTION SET DETAILS TGEIU TGEIU Trap If Greater Than Or Equal Immediate Unsigned 26 25 21 20 16 15 REGIMM TGEIU immediate 0 0 0 0 0 1 0 1 0 0 1 Format: TGEIU rs, immediate Description: The 16-bit immediate is sign-extended and compared to the contents of general register rs .
Page 575 APPENDIX A MIPS III INSTRUCTION SET DETAILS TGEU TGEU Trap If Greater Than Or Equal Unsigned 26 25 21 20 16 15 SPECIAL TGEU code 0 0 0 0 0 0 1 1 0 0 0 1 Format: TGEU rs, rt Description: The contents of general register rt are compared to the contents of general register rs .
Page 576 APPENDIX A MIPS III INSTRUCTION SET DETAILS TLBP TLBP Probe TLB For Matching Entry 26 25 COP0 TLBP 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 Format: TLBP...
Page 577 APPENDIX A MIPS III INSTRUCTION SET DETAILS TLBR TLBR Read Indexed TLB Entry 26 25 COP0 TLBR 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 Format: TLBR...
Page 578 APPENDIX A MIPS III INSTRUCTION SET DETAILS TLBWI TLBWI Write Indexed TLB Entry 26 25 COP0 TLBWI 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 Format: TLBWI...
Page 579 APPENDIX A MIPS III INSTRUCTION SET DETAILS TLBWR TLBWR Write Random TLB Entry 26 25 COP0 TLBWR 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 Format: TLBWR...
Page 580 APPENDIX A MIPS III INSTRUCTION SET DETAILS Trap If Less Than 26 25 21 20 16 15 SPECIAL code 0 0 0 0 0 0 1 1 0 0 1 0 Format: TLT rs, rt Description: The contents of general register rt are compared to general register rs . Considering both quantities as signed integers, if the contents of general register rs are less than the contents of general register rt , a trap exception occurs.
Page 581 APPENDIX A MIPS III INSTRUCTION SET DETAILS TLTI TLTI Trap If Less Than Immediate 26 25 21 20 16 15 REGIMM TLTI immediate 0 0 0 0 0 1 0 1 0 1 0 Format: TLTI rs, immediate Description: The 16-bit immediate is sign-extended and compared to the contents of general register rs . Considering both quantities as signed integers, if the contents of general register rs are less than the sign-extended immediate , a trap exception occurs.
Page 582 APPENDIX A MIPS III INSTRUCTION SET DETAILS TLTIU TLTIU Trap If Less Than Immediate Unsigned 26 25 21 20 16 15 REGIMM TLTIU immediate 0 0 0 0 0 1 0 1 0 1 1 Format: TLTIU rs, immediate Description: The 16-bit immediate is sign-extended and compared to the contents of general register rs .
Page 583 APPENDIX A MIPS III INSTRUCTION SET DETAILS TLTU TLTU Trap If Less Than Unsigned 26 25 21 20 16 15 SPECIAL TLTU code 0 0 0 0 0 0 1 1 0 0 1 1 Format: TLTU rs, rt Description: The contents of general register rt are compared to general register rs .
Page 584 APPENDIX A MIPS III INSTRUCTION SET DETAILS Trap If Not Equal 26 25 21 20 16 15 SPECIAL code 0 0 0 0 0 0 1 1 0 1 1 0 Format: TNE rs, rt Description: The contents of general register rt are compared to general register rs . If the contents of general register rs are not equal to the contents of general register rt , a trap exception occurs.
Page 585 APPENDIX A MIPS III INSTRUCTION SET DETAILS TNEI TNEI Trap If Not Equal Immediate 26 25 21 20 16 15 REGIMM TNEI immediate 0 0 0 0 0 1 0 1 1 1 0 Format: TNEI rs, immediate Description: The 16-bit immediate is sign-extended and compared to the contents of general register rs . If the contents of general register rs are not equal to the sign-extended immediate , a trap exception occurs.
Page 586 APPENDIX A MIPS III INSTRUCTION SET DETAILS Exclusive Or 26 25 21 20 16 15 11 10 SPECIAL 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 1 0 Format: XOR rd, rs, rt Description: The contents of general register rs are combined with the contents of general register rt in a bit-wise logical exclusive OR operation.
Page 587 APPENDIX A MIPS III INSTRUCTION SET DETAILS XORI XORI Exclusive OR Immediate 26 25 21 20 16 15 XORI immediate 0 0 1 1 1 0 Format: XORI rt, rs, immediate Description: The 16-bit immediate is zero-extended and combined with the contents of general register rs in a bit-wise logical exclusive OR operation.
Page 588: Cpu Instruction Opcode Bit Encoding
APPENDIX A MIPS III INSTRUCTION SET DETAILS A.6 CPU Instruction Opcode Bit Encoding Figure A-1 lists the V 4120A Opcode Bit Encoding. Figure A-1. V 4120A Opcode Bit Encoding (1/2) Opcode 28...26 31...29 SPECIAL REGIMM BLEZ BGTZ ADDI ADDIU SLTI SLTIU ANDI XORI...
Page 589 APPENDIX A MIPS III INSTRUCTION SET DETAILS Figure A-1. V 4120AOpcode Bit Encoding (2/2) COP0 rs 23...21 25, 24 γ γ γ γ DMFε DMTε γ γ γ γ γ γ γ COP0 rt 18...16 20...19 γ γ γ γ BCFL BCTL γ...
Page 590: Appendix B V R 4120A Coprocessor 0 Hazards
APPENDIX B V 4120A COPROCESSOR 0 HAZARDS The V 4120A core avoids contention of its internal resources by causing a pipeline interlock in such cases as when the contents of the destination register of an instruction are used as a source in the succeeding instruction. Therefore, instructions such as NOP must not be inserted between instructions.
Page 591 APPENDIX B V 4120A COPROCESSOR 0 HAZARDS Table B-1. V 4120A CPU Coprocessor 0 Hazards Operation Source Destination Source Name No. of Destination Name No. of Cycles Cycles MTC0 cpr rd MFC0 cpr rd TLBR Index, TLB PageMask, EntryHi, EntryLo0, EntryLo1 TLBWI Index or Random, PageMask,...
Page 592 APPENDIX B V 4120A COPROCESSOR 0 HAZARDS Remarks 1. The instruction following MTC0 must not be MFC0. 2. The five instructions following MTC0 to Status register that changes KSU and sets EXL and ERL may be executed in the new mode, and not kernel mode. This can be avoided by setting EXL first, leaving KSU set to kernel, and later changing KSU.
Page 593 APPENDIX B V 4120A COPROCESSOR 0 HAZARDS (10) Instruction Fetch Source: The confirmation of the operating mode and TLB necessary for instruction fetch. Examples 1. When changing the operating mode from User to Kernel and fetching instructions after the KSU, EXL, and ERL bits of the Status register are modified. When fetching instructions using the modified TLB entry after TLB modification.
Page 594: B-2 Calculation Example Of Cp0 Hazard And Number Of Instructions Inserted
APPENDIX B V 4120A COPROCESSOR 0 HAZARDS Table B-2 indicates examples of calculation. Table B-2. Calculation Example of CP0 Hazard and Number of Instructions Inserted Destination Source Contending Number of Formula Internal Instructions Resource Inserted TLBWR/TLBWI TLBP TLB Entry 5 – (2 + 1) TLBWR/TLBWI Load or Store using newly modified TLB TLB Entry...
Page 595 Facsimile Message Although NEC has taken all possible steps to ensure that the documentation supplied to our customers is complete, bug free and up-to-date, we readily accept that From: errors may occur. Despite all the care and precautions we've taken, you may Name encounter problems in the documentation.

NEC uPD98502 User Manual

Chapter 1 Introduction

Features

Ordering Information

System Configuration

Block Diagram (Summary)

Block Diagram (Detail)

Pin Configuration (Bottom View)

Pin Function

I/O Register Map

Memory Map

Reset Configuration

Interrupts

Clock Control Unit

Chapter 2 4120A

Overview for V R 4120A

MIPS III Instruction Set Summary

Pipeline

Memory Management System

Exception Processing

Initialization Interface

Cache Memory

CPU Core Interrupts

Chapter 3 System Controller

Overview

Registers

CPU Interface

Memory Interface

IBUS Interface

DSU (Deadman's SW Unit)

Endian Mode Software Issues

Chapter 4 Atm Cell Processor

Overview

Memory Space

Interruption

Registers for ATM Cell Processing

Data Structure

Initialization

Commands

Operations

Quick Links

Related Manuals for NEC uPD98502

Summary of Contents for NEC uPD98502