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3.1 Overview
Register map
This block is an internal system controller for the µ PD98502. System controller provides bridging function among
the CPU system bus "SysAD", NEC original high-speed on-chip bus "IBUS" and memory bus for SDRAM/PROM/flash.
Features of system controller are as follows.
• Provides bus bridging function among SysAD bus, IBUS and memory
• Supports endian converting function on SysAD bus
• Can directly connect to SDRAM and PROM/flash
• Supports Deadman's SW timer and separated 2-ch timers
• Supports NS16550 compatible UART
3.1.1 CPU interface
• Connects directly to the V
• Supports all V
4120A bus cycles at 66 MHz or 100 MHz
R
• Supports only data rate D
• Supports only sequential ordering
• 4-word (16-byte) x 4-entry write command buffer
• Little-endian or big-endian byte order
• Don't support 8-words burst R/W on SysAD bus
3.1.2 Memory interface
• 66-MHz or 100-MHz memory bus
• Up to 32-MB base memory range supports SDRAM
• Up to 8-MB write-protectable boot memory range supports PROM/flash
• On-chip programmable SDRAM refresh controller
• 4-word (16-byte) write data buffer
• 4-word (16-byte) prefetch data buffer (memory-to-CPU)
• PROM/flash data signals multiplexed on SDRAM data signals
• Variable Flash memory data bus (8,16,32 bits)
• Programmable memory bus arbitration priority
• Programmable address ranges for the memory
• Programmable RAS-CAS delay (2, 3, 4 clocks)
• Programmable CAS latency (2, 3 clocks)
3.1.3 IBUS Interface
• Master and target capability
• 64-word (256-byte) IBUS Slave TxFIFO (IBUS reads data from memory)
• 64-word (256-byte) IBUS Slave RxFIFO (IBUS writes data to memory)
• 4-word (16-byte) IBUS Master TxFIFO (V
• 4-word (16-byte) x 4 entry IBUS Master RxFIFO (V
• Supports bus timer to detect IBUS stall
CHAPTER 3 SYSTEM CONTROLLER
4120A CPU bus "SysAD bus"
R
4120A reads data from IBUS)
R
4120A writes data to IBUS)
R
Preliminary User's Manual S15543EJ1V0UM
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