NEC uPD98502 User Manual page 312

2. All internal registers are 32-bit word-aligned registers.
3. The burst access to the internal register is prohibited.
If such burst access has been occurred, IRERR bit in NSR is set and NMI will assert to CPU.
4. Read access to the reserved area will set the CBERR bit in the NSR register and the dummy read
response data with the data-error bit set on SysCMD [0] is returned.
5. Write access to the reserved area will set the CBERR bit in the NSR register, and the write data is lost.
6. In the "Access" filed,
"W" means that word access is valid,
"H" means that half word access is valid,
"B" means that byte access is valid.
7. Write access to the read-only register cause no error, but the write data is lost.
8. The CPU can access all internal registers, but IBUS master device cannot access them.
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CHAPTER 6 USB CONTROLLER
Preliminary User's Manual S15543EJ1V0UM