Masking Of Interrupt Request Signals - NEC uPD98502 User Manual

2.8.5.2 Masking interrupt signals
Figure 2-89 shows the masking of the CPU core interrupt signals.
Cause register bits 15 to 8 (IP7 to IP0) are AND-ORed with Status register interrupt mask bits 15 to 8 (IM7 to
IM0) to mask individual interrupts.
Status register bit 0 is a global Interrupt Enable (IE). It is ANDed with the output of the AND-OR logic shown
in Figure 2-89 to produce the CPU core interrupt signal. The EXL bit in the Status register also enables
these interrupts.
Software interrutpts
generated in CPU core
Timer interrupt
Bit
IE
IM(7:0)
IP(7:0)
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CHAPTER 2 V
Figure 2-89. Masking of Interrupt Request Signals
Status register
SR0
IE
Status register
SR (15:8)
IM0
8
IM1
9
IM2
10
8
IM3
11
IM4
12
IM5
13
IM6
14
IM7
15
IP0
8
IP1
9
IP2
10
8
IP3
11
Ordinary
IP4
12
interrupts
IP5
13
IP6
14
AND-OR block
IP7
15
Cause register
(15:8)
Function
Whole interrupts enable
Interrupt mask
Interrupt request
Preliminary User's Manual S15543EJ1V0UM
4120A
R
CPU core interrupt
1
1
AND block
Setting
1 : Enable
0 : Disable
Each bit 1 : Enable
0 : Disable
Each bit 1 : Pending
0 : Not pending