Dma And Fifo Management Registers Map - NEC uPD98502 User Manual

5.2.1.3 DMA and FIFO management registers
These registers control to transfer receive and transmit data by internal DMAC of this block.
Offset Address Register Name
1000_m200H En_TXCR
1000_m204H En_TXFCR
1000_m208H: N/A
1000_m210H
1000_m214H En_TXDPR
1000_m218H En_RXCR
1000_m21CH En_RXFCR
1000_m220H: N/A
1000_m228H
1000_m22CH En_RXDPR
1000_m230H En_RXPDR
Remarks 1. In the "Offset Address" field and in the "Register Name" field,
Ethernet Controller #1: m = 2, n = 1,
Ethernet Controller #2: m = 3, n = 2
2. In the "R/W" field,
"W" means "writeable",
"R" means "readable",
"RC" means "read-cleared",
"- " means "not accessible".
3. All internal registers are 32-bit word-aligned registers.
4. The burst access to the internal register is prohibited.
If such burst access has been occurred, IRERR bit in NSR is set and NMI will assert to CPU.
5. Read access to the reserved area will set the CBERR bit in the NSR register and the dummy read
response data with the data-error bit set on SysCMD [0] is returned.
6. Write access to the reserved area will set the CBERR bit in the NSR register, and the write data is lost.
7. In the "Access" filed,
"W" means that word access is valid,
"H" means that half word access is valid,
"B" means that byte access is valid.
8. Write access to the read-only register cause no error, but the write data is lost.
9. The CPU can access all internal registers, but IBUS master device cannot access them.
CHAPTER 5 ETHERNET CONTROLLER
Table 5-4. DMA and FIFO Management Registers Map
R/W Access
R/W W
R/W W
- -
R/W W
R/W W
R/W W
- -
R/W W
R/W W
Preliminary User's Manual S15543EJ1V0UM
Description
Transmit Configuration Register
Transmit FIFO Control Register
Reserved for future use
Transmit Descriptor Register
Receive Configuration Register
Receive FIFO Control Register
Reserved for future use
Receive Descriptor Register
Receive Pool Descriptor Register
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