Three-Operand Type Instruction (Extended Isa); Shift Instruction - NEC uPD98502 User Manual

Table 2-9. Three-Operand Type Instruction (Extended ISA)
Instruction
Doubleword Add DADD rd, rt, rs
The contents of register rs are added to that of register rt. The 64-bit result is stored into register rd.
An exception occurs on the generation of integer overflow.
Doubleword Add DADDU rd, rt, rs
Unsigned
The contents of register rs are added to that of register rt. The 64-bit result is stored into register rd.
No exception occurs on the generation of integer overflow.
Doubleword Subtract DSUB rd, rt, rs
The contents of register rt are subtracted from that of register rs. The 64-bit result is stored into
register rd.
An exception occurs on the generation of integer overflow.
Doubleword Subtract DSUBU rd, rt, rs
Unsigned The contents of register rt are subtracted from that of register rs. The 64-bit result is stored into
register rd.
No exception occurs on the generation of integer overflow.
Instruction
Shift Left Logical SLL rd, rs, sa
The contents of register rt are shifted left by sa bits and zeros are inserted into the emptied lower bits.
The 32-bit result is stored into register rd. In the 64-bit mode, the operand must be sign extended.
Shift Right Logical SRL rd, rs, sa
The contents of register rt are shifted right by sa bits and zeros are inserted into the emptied higher
bits.
The 32-bit result is stored into register rd. In the 64-bit mode, the operand must be sign extended.
Shift Right Arithmetic SRA rd, rt, sa
The contents of register rt are shifted right by sa bits and the emptied higher bits are sign extended.
The 32-bit result is stored into register rd. In the 64-bit mode, the operand must be sign extended.
Shift Left Logical SLLV rd, rt, rs
Variable The contents of register rt are shifted left and zeros are inserted into the emptied lower bits. The lower
five bits of register rs specify the shift count.
The 32-bit result is stored into register rd. In the 64-bit mode, the operand must be sign extended.
Shift Right Logical SRLV rd, rt, rs
Variable The contents of register rt are shifted right and zeros are inserted into the emptied higher bits. The
lower five bits of register rs specify the shift count.
The 32-bit result is stored into register rd. In the 64-bit mode, the operand must be sign extended.
Shift Right Arithmetic SRAV rd, rt, rs
Variable The contents of register rt are shifted right and the emptied higher bits are sign extended. The lower
five bits of register rs specify the shift count.
The 32-bit result is stored into register rd. In the 64-bit mode, the operand must be sign extended.
CHAPTER 2 V
Format and Description
Table 2-10. Shift Instruction
Format and Description
Preliminary User's Manual S15543EJ1V0UM
4120A
R
op rs rt
op rs rt
rd sa
funct
rd sa
funct
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