Interlock And Exception Handling; Relationship Among Interlocks, Exceptions, And Faults; Correspondence Of Pipeline Stage To Interlock And Exception Conditions - NEC uPD98502 User Manual

2.3.5 Interlock and exception handling

Smooth pipeline flow is interrupted when cache misses or exceptions occur, or when data dependencies are
detected. Interruptions handled using hardware, such as cache misses, are referred to as interlocks, while those that
are handled using software are called exceptions. As shown in Figure 2-19, all interlock and exception conditions are
collectively referred to as faults.
Figure 2-19. Relationship among Interlocks, Exceptions, and Faults
At each cycle, exception and interlock conditions are checked for all active instructions.
Because each exception or interlock condition corresponds to a particular pipeline stage, a condition can be traced
back to the particular instruction in the exception/interlock stage, as shown in Table 2-23. For instance, an LDI
Interlock is raised in the Register Fetch (RF) stage.
Tables 2-24 and 2-25 describe the pipeline interlocks and exceptions listed in Table 2-23.
Table 2-23. Correspondence of Pipeline Stage to Interlock and Exception Conditions
Status
Interlock Stall
Slip
Exception
Remark In the above table, exception conditions are listed up in higher priority order.
94
CHAPTER 2 V
Faults
Software
Exceptions
Abort
Stage IF
−
−
IAErr
Preliminary User's Manual S15543EJ1V0UM
4120A
R
Hardware
Interlocks
Stall Slip
RF EX
(IT)
−
ITM
ICM
−
LDI
MDI
SLI
CP0
NMI Trap
ITLB OVF
IPErr DAErr
INTr
IBE
SYSC
BP
CUn
RSVD
DC WB
−
DTM
DCM
DCB
− −
−
Reset
DTLB
TMod
DPErr
WAT
DBE