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DSRL
31
26 25
SPECIAL
0 0 0 0 0 0
6
Format:
DSRL rd, rt, sa
Description:
The contents of general register rt are shifted right by sa bits, inserting zeros into the high-order bits. The result is
placed in register rd .
This operation is defined in 64-bit mode or in 32-bit kernel mode. Execution of this instruction in 32-bit user or
supervisor mode causes a reserved instruction exception.
Operation:
s ← 0 || sa
64
T:
GPR [rd] ← 0
Exceptions:
Reserved instruction exception (32-bit user mode/supervisor mode)
490
APPENDIX A MIPS III INSTRUCTION SET DETAILS
Doubleword Shift Right Logical
21 20
0
rt
0 0 0 0 0
5
5
s
|| GPR [rt]
63..s
Preliminary User's Manual S15543EJ1V0UM
16 15
11 10
rd
5
DSRL
6 5
DSRL
sa
1 1 1 0 1 0
5
6
0
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