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LDL
31
26 25
LDL
0 1 1 0 1 0
6
Format:
LDL rt, offset (base)
Description:
This instruction can be used in combination with the LDR instruction to load a register with eight consecutive bytes
from memory, when the bytes cross a doubleword boundary. LDL loads the left portion of the register with the
appropriate part of the high-order doubleword; LDR loads the right portion of the register with the appropriate part
of the low-order doubleword.
The LDL instruction adds its sign-extended 16-bit offset to the contents of general register base to form a virtual
address that can specify an arbitrary byte. It reads bytes only from the doubleword in memory that contains the
specified starting byte. From one to eight bytes will be loaded, depending on the starting byte specified.
Conceptually, it starts at the specified byte in memory and loads that byte into the high-order (left-most) byte of the
register; then it loads bytes from memory into the register until it reaches the low-order byte of the doubleword in
memory. The least-significant (right-most) byte(s) of the register will not be changed.
15 14 13 12 11 10
address 8
address 0
7
6
APPENDIX A MIPS III INSTRUCTION SET DETAILS
Load Doubleword Left (1/3)
21 20
base
rt
5
5
memory
9
8
5
4
3
2
1
0
LDL $24, 12 ($0)
Preliminary User's Manual S15543EJ1V0UM
16 15
before
A
B
C
after
12 11 10
LDL
offset
16
register
$24
D
E
F
G
H
$24
9
8
F
G
H
0
505
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