NEC uPD98502 User Manual page 408

7.5.19.14 Subsystem ID register
This register is used to uniquely identify the expansion board or subsystem where the PCI device resides.
Bits Field
15:0 Subsystem ID
7.5.19.15 Cap_Ptr register
This register is used to show a linked list of new capabilities implemented by The PCI Controller. The PCI
Controller has PPMI function as a new capability. Its data structure starts from '40H' in the configuration register.
Bits Field
7:0 Capabilities
Pointer
7.5.19.16 Interrupt line register
The Interrupt Line register is used to communicate interrupt line routing information.
Bits Field
7:0 Interrupt Line
7.5.19.17 Interrupt pin register
This register tells which interrupt pin the PCI Controller uses.
Bits Field
7:0 Interrupt Pin
7.5.19.18 Min_Gnt register
This register specifies how long a burst period the PCI Controller needs assuming a clock rate of 33MHz.
Bits Field
7:0 Min_Gnt
408
CHAPTER 7 PCI CONTROLLER
R/W Default
Internal PCI
bus
R/W R 0
R/W Default
Internal PCI
bus
R R 40H
R/W Default
Internal PCI
bus
R/W R/W 0
R/W Default
Internal PCI
bus
R R 01H
R/W Default
Internal PCI
bus
R/W R 0
Preliminary User's Manual S15543EJ1V0UM
Description
The V 4120A should set the identifier to this register.
R
Description
Hardwired to '40H', where is the first term of the new capabilities
list.
Description
The value in this register shows the input of the system interrupt
controller that the interrupt pin is connected.
Description
Hardwired to '01H', which means the PCI Controller uses INTA_B
pin.
Description
The user of the PCI Controller must prepare the value to this
register. The value should be set by the V 4120A.
R