NEC uPD98502 User Manual page 413

- Sets a '1' to "Bus Master Enable" bit in command register, if the chip executes transaction as PCI-master
- Sets a '1' to "Memory Write and Invalidate Enable" bit in command register, if needed
- Sets a '1' to "Parity Error Response" bit in command register, if needed
- Sets a '1' to "System Error Response " bit in command register, if needed
- Sets a the cache line size of system to "Cache Line Size" register
- Sets a "Latency Timer" register, if needed
- Sets base addresses to "Window Base Memory Address" register and "Register Base Memory Address"
register
Initialization for internal registers is as follows;
-Sets base addresses to P_PLBA register and P_IBBA register
-Enables mask bits in P_IIMR register, if needed
-Sets arbiter mode by PARBM bit in P_HMCR register, if needed
-Sets which command the PCI Controller uses on Internal bus, I/O or memory, by ICMDS bit in P_BCNT
register
-Sets which the PCI Controller uses DAC on PCI bus or not, by DACEN bit in P_BCNT register
-Sets data transfer mode by PDRTD bit, PPWRD bit, IDRTD bit, IPWRD bit in P_BCNT register.
-Sets '00' to PowerState field in PMCSR register in order to indicate that chip can be run.
-Sets a '1' to INITD bit in P_BCNT register in order to indicate that the Initialization of the PCI Controller has
been completed.
After the time INITD bit is set, the PCI Controller can accepts the access from PCI-side.
(1) Error
If Error described in 7.2.3 Abnormal Termination occurs, the PCI Controller sets bits in Status register of
configuration space, P_IGSR register and P_PGSR register, and issues interrupts to the V
PCI-Host device (if not masked). The V
The PCI Controller would stop the current transaction, and returns to the state in which the PCI Controller can accept
new accesses.
CHAPTER 7 PCI CONTROLLER
4120A and PCI-Host are responsible for how to handle these error statuses.
R
Preliminary User's Manual S15543EJ1V0UM
4120A and an external
R
413