Table of Contents
Advertisement
MACC
31
26 25
SPECIAL
0 0 0 0 0 0
6
Format:
MACC rd, rs, rt
MACCU rd, rs, rt
MACCHI rd, rs, rt
MACCHIU rd, rs, rt
MACCS rd, rs, rt
MACCUS rd, rs, rt
MACCHIS rd, rs, rt
MACCHIUS rd, rs, rt
Description:
MACC instruction differs mnemonics by each setting of op codes sat, hi and us as follows.
MACC
MACCU
MACCHI
MACCHIU
MACCS
MACCUS
MACCHIS
MACCHIUS
The number of significant bits in the operands of the MACC instruction differ depending on whether saturation
processing is executed (sat = 1) or not executed (sat = 0).
•
When saturation processing is executed (sat = 1): MACCS, MACCUS, MACCHIS, MACCHIUS instructions
The contents of general register rs is multiplied by the contents of general register rt . If both operands are set
as "us = 1" (MACCUS, MACCHIUS instructions), the contents are handled as 16-bit unsigned data. If they are
set as "us = 0" (MACCS, MACCHIS instructions), the contents are handled as 16-bit signed integers.
Sign/zero expansion by software is required for any bits exceeding 16 bits in the operands. The product of this
multiply operation is added to a 64-bit value (of which only the low-order 32 bits are valid) that is linked to the
HI and LO special registers. If us = 1, this add operation handles the values being added as 32-bit unsigned
data. If us = 0, the values are handled as 32-bit signed integers. Sign/zero expansion by software is required
for any bits exceeding 32 bits in the linked HI and LO special registers. After saturation processing to 32 bits
has been performed (see the table below), the sum from this add operation is loaded to the HI and LO special
register. When hi = 1 (MACCHIS, MACCHIUS instructions), data that is the same as the data loaded to the HI
special register is also loaded to the rd general register. When hi = 0 (MACCS, MACCUS instructions), data
that is the same as the data loaded to the LO special register is also loaded to the rd general register.
Overflow exceptions do not occur.
522
APPENDIX A MIPS III INSTRUCTION SET DETAILS
Multiply and Accumulate (1/5)
21 20
rs
rt
5
5
Mnemonic
sat
0
0
0
0
1
1
1
1
Preliminary User's Manual S15543EJ1V0UM
16 15
11 10
9
rd
sat
hi
5
1
1
hi
0
0
1
1
0
0
1
1
MACC
8
7
6 5
MACC
0 0
us
1 0 1 0 0 0
2
6
1
us
0
1
0
1
0
1
0
1
0
Advertisement
Table of Contents
