U_Ep0Cr (Usb Ep0 Control Register) - NEC uPD98502 User Manual

6.2.8 U_EP0CR (USB EP0 Control Register)

This register is used for setting the operation of EndPoint0.
If the value in the MAXP field is rewritten during transmitting or receiving operation, the operation of USB Controller
may become unpredictable. Therefore, the MAXP can be written only when initial setting is being performed.
Bits Field
31 EP0EN
30:19 Reserved
20 ISS
19 INAK
18 OSS
17 NHSK0
16 ONAK
15:7 Reserved
6:0 MAXP0
Remark When a STALL handshake is sent by a control endpoint in either the Data or Status stage of a control
transfer, a STALL handshake must be returned on all succeeding access to that endpoint until a SETUP
PID is received. The endpoint is not required to return a STALL handshake after it receives a subsequent
SETUP PID (referred from USB1.1 Specification).
320
CHAPTER 6 USB CONTROLLER
R/W Default
R/W 0 EndPoint Enable:
When the V
and receiving data to and from USB.
R/W 0 Reserved for future use. Writes '0's.
R/W 0 IN Transmit Stall:
When the V
Phase.
Receiving a SETUP packet causes this bit to be a '0'.
R/W 0 IN NAK:
When the V
Phase.
R/W 0 OUT Transmit Stall:
When the V
the Handshake Phase.
Receiving a SETUP packet causes this bit to be a '0'
R/W 0 No Handshake:
When the V
Handshake Phase.
R/W 0 OUT NAK:
When the V
Handshake Phase.
R/W 0 Reserved for future use. Writes '0's.
R/W 0 MAX Packet size:
The Max Packet Size for EndPoint0. Prior to the start of a USB transaction,
the V 4120A must set an appropriate value into this register.
R
Preliminary User's Manual S15543EJ1V0UM
Description
4120A sets this bit to a '1', EndPoint0 is enabled for transmitting
R
4120A sets this bit to a '1', a STALL packet is sent at the Data
R
4120A sets this bit to a '1', a NAK packet is sent at the Data
R
4120A sets this bit to a '1', a STALL handshake is performed at
R
4120A sets this bit to a '1', No Handshake is performed at the
R
4120A sets this bit to a '1,' NAK Handshake is performed at the
R