Cause Register Exception Code Field - NEC uPD98502 User Manual

Exception Code
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14 to 22
23
24 to 31
The V 4120A CPU has eight interrupt request sources, IP7 to IP0. For the detailed description of interrupts, refer
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to Section 2.8 CPU Core Interrupts.
(1) IP7
This bit indicates whether there is a timer interrupt request.
It is set when the values of Count register and Compare register match.
(2) IP6 to IP2
IP6 to IP2 reflect the state of the interrupt request signal of the CPU core.
(3) IP1 and IP0
These bits are used to set/clear a software interrupt request.
CHAPTER 2 V
Table 2-35. Cause Register Exception Code Field
Mnemonic
Int Interrupt exception
Mod TLB Modified exception
TLBL TLB Refill exception (load or fetch)
TLBS TLB Refill exception (store)
AdEL Address Error exception (load or fetch)
AdES Address Error exception (store)
IBE Bus Error exception (instruction fetch)
DBE Bus Error exception (data load or store)
Sys System Call exception
Bp Breakpoint exception
RI Reserved Instruction exception
CpU Coprocessor Unusable exception
Ov Integer Overflow exception
Tr Trap exception

RFU
WATCH Watch exception

RFU
Preliminary User's Manual S15543EJ1V0UM
4120A
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Description
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