NEC uPD98502 User Manual page 50

Core Offset
PCI 048H-04CH
PCI 050H
PCI 054H
PCI 058H
PCI 05CH
PCI 060H-0FFH
PCI 100H-1FFH
Ether 00H
Ether 04H
Ether 08H
Ether 0CH
Ether 10H
Ether 14H
Ether 18H-1CH
Ether 20H
Ether 24H-50H
Ether 54H
Ether 58H
Ether 5CH
Ether 60H
Ether 64H
Ether 80H
Ether 84H-90H
Ether 94H
Ether 98H
Ether 9CH
Ether A0H
Ether A4H
Ether A8H-C4H
Ether CCH
Ether D0H
Ether D4H-D8H
Ether DCH
Ether E0H
Ether E4H-12CH
Ether 130H
Ether 134H
Ether 138H-13CH
Ether 140H
Ether 144H
Ether 148H
Ether 14CH
Ether 150H
Ether 154H
Ether 158H
Ether 15CH
Ether 160H
Ether 164H
Ether 168H
Ether 16CH
Ether 170H
Ether 174H
Ether 178H
Ether 17CH
Ether 180H
Ether 184H
Ether 188H
Ether 18CH
Ether 190H
Ether 194H
Ether 198H
Ether 1C0H
Ether 1C4H
Ether 1C8H
Ether 1CCH
50
CHAPTER 1 INTRODUCTION
Register Name Access by
Length V
(Byte)
4 N/A -
4 P_BCNT R/W
4 P_PPCR R/W
4 P_SWRR W
4 P_PTMR R/W
4 N/A -
4 P_CONFIG (*)
4 En_MACC1 R/W
4 En_MACC2 R/W
4 En_IPGT R/W
4 En_IPGR R/W
4 En_CLRT R/W
4 En_LMAX R/W
- N/A -
4 En_RETX R/W
- N/A -
4 En_LSA2 R/W
4 En_LSA1 R/W
4 En_PTVR R
- N/A -
4 En_VLTP R/W
4 En_MIIC R/W
- N/A -
4 En_MCMD W
4 En_MADR R/W
4 En_MWTD R/W
4 En_MRDD R
4 En_MIND R
- N/A -
4 En_HT1 R/W
4 En_HT2 R/W
- N/A -
4 En_CAR1 R/W
4 En_CAR2 R/W
- N/A -
4 En_CAM1 R/W
4 En_CAM2 R/W
- N/A -
4 En_RBYT R/W
4 En_RPKT R/W
4 En_RFCS R/W
4 En_RMCA R/W
4 En_RBCA R/W
4 En_RXCF R/W
4 En_RXPF R/W
4 En_RXUO R/W
4 En_RALN R/W
4 En_RFLR R/W
4 En_RCDE R/W
4 En_RFCR R/W
4 En_RUND R/W
4 En_ROVR R/W
4 En_RFRG R/W
4 En_RJBR R/W
4 En_R64 R/W
4 En_R127 R/W
4 En_R255 R/W
4 En_R511 R/W
4 En_R1K R/W
4 En_RMAX R/W
4 En_RVBT R/W
4 En_TBYT R/W
4 En_TPCT R/W
4 En_TFCS R/W
4 En_TMCA R/W
Preliminary User's Manual S15543EJ1V0UM
4120A
R
Reserved for future use
Bridge Control Register
Power Control Register
Software Reset Register
Retry Timer Register
Reserved for future use
Configuration Registers.
* Some registers are R/W. Other registers are Read only.
MAC configuration register 1
MAC configuration register 2
Back-to-Back IPG register
Non Back-to-Back IPG register
Collision register
Max packet length register
Reserved for future use
Retry count register
Reserved for future use
Station Address register 2
Station Address register 1
Pause timer value read register
Reserved for future use
VLAN type register
MII configuration register
Reserved for future use
MII command register
MII address register
MII write data register
MII read data register
MII indicator register
Reserved for future use
Hash table register 1
Hash table register 2
Reserved for future use
Carry register 1
Carry register 2
Reserved for future use
Carry mask register 1
Carry mask register 2
Reserved for future use
Receive Byte Counter
Receive Packet Counter
Receive FCS Error Counter
Receive Multicast Packet Counter
Receive Broadcast Packet Counter
Receive Control Frame Packet Counter
Receive PAUSE Frame Packet Counter
Receive Unknown OP code Counter
Receive Alignment Error Counter
Receive Frame Length Out of Range Counter
Receive Code Error Counter
Receive False Carrier Counter
Receive Undersize Packet Counter
Receive Oversize Packet Counter
Receive Error Undersize Packet Counter
Receive Error Oversize Packet Counter
Receive 64 Byte Frame Counter
Receive 65 to 127 Byte Frame Counter
Receive 128 to 255 Byte Frame Counter
Receive 256 to 511 Byte Frame Counter
Receive 512 to 1023 Byte Frame Counter
Receive Over 1023 Byte Frame Counter
Receive Valid Byte Counter
Transmit Byte Counter
Transmit Packet Counter
Transmit CRC Error Packet Counter
Transmit Multicast Packet Counter
Description