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5.2.35 En_MSR (Mask Serves Register)
Each interrupt source is maskable. En_MSR register shows which interrupts are enable.
Default value is all "0" which means all interrupt sources are disable.
Bits
Field
31:16
Reserved
15
XMTDN
14
TBDR
13
TFLE
12
UR
11
TABR
9:8
Reserved
10
TCFRI
7
RCVDN
6
RBDRS
5
RBDRU
4
OF
3
LFAL
2:1
Reserved
0
CARRY
CHAPTER 5 ETHERNET CONTROLLER
R/W
Default
R/W
0
Reserved for future use. Write 0s.
R/W
0
Transmit Done
R/W
0
Transmit Buffer Descriptor Request at Null
R/W
0
Transmit Frame Length Exceed
R/W
0
Underrun
R/W
0
Transmit Aborted
R/W
0
Reserved for future use. Write 0s.
R/W
0
Control Frame Transmit
R/W
0
Receive Done
R/W
0
Receive Buffer Descriptor Request at alert level
R/W
0
Receive Buffer Descriptor Request at zero
R/W
0
Overflow
R/W
0
Link Failed
R/W
0
Reserved for future use. Write 0s.
R/W
0
Carry Flag:
CARRY indicates an overflow of the statistics counters
Preliminary User's Manual S15543EJ1V0UM
Description
299
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