P_Pimr (Pci Interrupt Mask Register) - NEC uPD98502 User Manual

7.5.11 P_PIMR (PCI Interrupt Mask Register)

PIMR register masks interruptions. A mask bit, which locates in the same bit position to a corresponding bit in
PGSR, can mask the interruption. When a bit of this register is reset to '0', the corresponding bit of the PGSR is
masked. When it is set to '1', the corresponding bit is unmasked. When the mask bit is reset and the bit in PGSR is
set, the PCI Controller sets the interrupt signal to PCI-Host.
Bits Field
31:16 PUINT
15:11 Reserved
10 IPREQ
9 SWRDN
8 DPERR
7 SSERR
6 RMABT
5 RTABT
4 STABT
3 PFDSC
2 RTYTE
1 PRBER
0 PWBER
CHAPTER 7 PCI CONTROLLER
R/W Default
Internal PCI
bus
R/W R/W 0
- - 0
R/W R/W 0
R/W R/W 0
R/W R/W 0
R/W R/W 0
R/W R/W 0
R/W R/W 0
R/W R/W 0
R/W R/W 0
R/W R/W 0
R/W R/W 0
R/W R/W 0
Preliminary User's Manual S15543EJ1V0UM
Description
Mask bits for the Interrupts defined by the system the chip is
used.
'0' means masked.
'1' means unmasked.
Hardwired to '0's.
Mask bit for the state transition for PPMI.
'0' means masked.
'1' means unmasked.
Mask bit for Software Reset done.
'0' means masked.
'1' means unmasked.
Mask bit for Detected Parity Error.
'0' means masked.
'1' means unmasked.
Mask bit for Signaled SERR_B.
'0' means masked.
'1' means unmasked.
Mask bit for Received Master Abort.
'0' means masked.
'1' means unmasked.
Mask bit for Received Target Abort.
'0' means masked.
'1' means unmasked.
Mask bit for Signaled Target Abort.
'0' means masked.
'1' means unmasked.
Mask bit for the discard of data in PCI FIFO.
'0' means masked.
'1' means unmasked.
Mask bit for Retry Timer Expired.
'0' means masked.
'1' means unmasked.
Mask bit for internal bus Error in read transaction.
'0' means masked.
'1' means unmasked.
Mask bit for internal bus Error in write transaction.
'0' means masked.
'1' means unmasked.
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