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TLBP
31
26 25
COP0
CO
0 1 0 0 0 0
1
6
1
Format:
TLBP
Description:
The Index register is loaded with the address of the TLB entry whose contents match the contents of the EntryHi
register. If no TLB entry matches, the high-order bit of the Index register is set.
The architecture does not specify the operation of memory references associated with the instruction immediately
after a TLBP instruction, nor is the operation specified if more than one TLB entry matches.
Operation:
Index ← 1 || 0
32
T:
for i in 0...TLBEntries - 1
if (TLB [i]
(TLB [i]
endif
endfor
Index ← 1 || 0
64
T:
for i in 0...TLBEntries - 1
if (TLB [i]
= (EntryHi
(TLB [i]
endif
endfor
Exceptions:
Coprocessor unusable exception
576
APPENDIX A MIPS III INSTRUCTION SET DETAILS
Probe TLB For Matching Entry
24
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
25
6
|| Undefined
= EntryHi
) and (TLB [i]
95...77
31...13
= EntryHi
)) then
71...64
7...0
26
Index ← 0
|| i
5...0
25
6
|| Undefined
15
and not (0
|| TLB [i]
167...141
15
) and not (0
|| TLB [i]
39...13
or (TLB [i]
= EntryHi
140
135...128
26
Index ← 0
|| i
5...0
Preliminary User's Manual S15543EJ1V0UM
0
19
or
76
))
216...205
)) and
216...205
)) then
7...0
TLBP
6 5
0
TLBP
0 0 1 0 0 0
6
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