NEC uPD98433 Preliminary User's Manual
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NEC uPD98433 Preliminary User's Manual

NEC uPD98433 Preliminary User's Manual

10/100/1000 mbps ethernet controller
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Preliminary User's Manual
µ
PD98433
10/100/1000 Mbps Ethernet
Document No. S15212EJ3V0UM00 (3rd edition)
Date Published September 2003 NS CP(K)
Printed in Japan
2001
TM
Controller

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  • Page 1 Preliminary User’s Manual µ PD98433 10/100/1000 Mbps Ethernet Controller Document No. S15212EJ3V0UM00 (3rd edition) Date Published September 2003 NS CP(K) 2001 Printed in Japan...
  • Page 2 [MEMO] Preliminary User’s Manual S15212EJ3V0UM...
  • Page 3 NOTES FOR CMOS DEVICES PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred.
  • Page 4 NEC Electronics does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of NEC Electronics products listed in this document or any other liability arising from the use of such products. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Electronics or others.
  • Page 5 Major Revisions in This Edition Page Description pp. 13 to 15 1.3 Pin Configuration Modified the names of pins No. 64 (AP31), 359 (C17), and 428 (AK31). p. 17 Changed the figure of 1.5 Sample System Configuration pp. 18, 22, 24, 27 CHAPTER 2 PIN FUNCTIONS Modified the description of the pins;...
  • Page 6 PREFACE µ Target Readers This manual is intended for users who wish to understand the functions of the PD98433 and to design and develop systems using it. Purpose This manual is intended to give users an understanding of the hardware functions of the µ...

  • Page 7: Table Of Contents

    CONTENTS CHAPTER 1 OVERVIEW..........................11 Features ............................11 Ordering Information ........................11 Pin Configuration........................12 Internal Block Diagram.......................17 Sample System Configuration....................17 CHAPTER 2 PIN FUNCTIONS........................18 CHAPTER 3 FUNCTION DESCRIPTION....................28 System Configuration.........................28 Function Blocks ..........................29 3.2.1 MAC module ..........................29 3.2.2 PCS module........................... 30 3.2.3 Station Address Logic (SAL) module .....................
  • Page 8 3.8.4 MII management interface......................54 µ 3.8.5 PD98433 connection of MII output signal pins ................56 3.8.6 Auto-negotiation ..........................56 Flow Control ..........................57 3.9.1 Control frame reception........................57 3.9.2 Flow control pause timer ........................57 3.9.3 Pause control frame transmission ....................58 3.10 Back Pressure ..........................61 3.11 Operations on VLAN Frames .....................61 3.11.1 VLAN frame detection ........................61...
  • Page 9 LIST OF FIGURES Figure No. Title Page µ Sample System Configuration Using PD98433 .................... 28 µ PD98433 Function Block Diagram........................ 29 Ethernet/IEEE802.3 Frame Structure ......................32 VLAN Frame Structure ........................... 32 Configuration of Status and RBYT Fields ....................... 39 FIFO Interface Write Timing ........................... 42 Timing of Switching Transmit Data Write Port Using TXFPT[2:0]..............
  • Page 10 LIST OF TABLES Title Page Receive Status Information..........................40 RBYT Field ..............................41 TXFDQ Pins and Transmit Data Attributes .....................43 RXFDQ Pins and Receive Data Attributes......................46 CLKS Field of MIIC Register and Frequency of MDC..................54 Pause Order of Precedence Resolution Table....................107 Operation in Each Controller State .......................137 Preliminary User’s Manual S15212EJ3V0UM...

  • Page 11: Chapter 1 Overview

    CHAPTER 1 OVERVIEW µ PD98433 is a 10/100/1000 Mbps Ethernet controller with an eight-port on-chip Media Access Control (MAC) function compliant with IEEE Standard 802.3 1998 Edition. Its main features are as follows. Features • 8-port 10/100/1000 Mbps on-chip MAC compliant with IEEE Standard 802.3 1998 Edition •...

  • Page 12: Pin Configuration

    CHAPTER 1 OVERVIEW Pin Configuration µ PD98433 756-pin plastic BGA Top view Index mark µ PD98433 756-pin plastic BGA Bottom view Index mark Preliminary User’s Manual S15212EJ3V0UM...
  • Page 13 CHAPTER 1 OVERVIEW (1/4) Pin No. Pin Name Pin No. Pin Name Pin No. Pin Name Pin No. Pin Name 1 (A1) 51 (AP18) RXFDQ0 101 (A33) 151 (Y2) TXD24 2 (B1) 52 (AP19) RXFCK 102 (A32) 152 (AA2) TX_ER2 3 (C1) 53 (AP20) 103 (A31)
  • Page 14 CHAPTER 1 OVERVIEW (2/4) Pin No. Pin Name Pin No. Pin Name Pin No. Pin Name Pin No. Pin Name 201 (AG33) GTX_CLK4 251 (B8) TXFD12 301 (AM18) RXFDQ2 351 (C25) TXFD99 202 (AF33) TXD44 252 (B7) TXFD6 302 (AM19) RXFD65 352 (C24) TXFD94 203 (AE33) RXD50...
  • Page 15 CHAPTER 1 OVERVIEW (3/4) Pin No. Pin Name Pin No. Pin Name Pin No. Pin Name Pin No. Pin Name 401 (AL5) RXETH5 451 (G31) 501 (AE5) TXD33 551 (K30) RXD71 402 (AL6) RXFD1 452 (F31) TXD77 502 (AF5) TXD36 552 (J30) RXD74 403 (AL7)
  • Page 16 CHAPTER 1 OVERVIEW (4/4) Pin No. Pin Name Pin No. Pin Name Pin No. Pin Name Pin No. Pin Name 601 (AF6) TXD35 651 (F28) TXFD119 701 (AH14) VDDQ 751 (G13) 602 (AG6) GTX_CLK3 652 (F27) TXFD113 702 (AH15) GND 752 (G12) 603 (AH6) RXD31...

  • Page 17: Internal Block Diagram

    CHAPTER 1 OVERVIEW Internal Block Diagram GMII ×8 PORT #7 PORT #6 PORT #5 PORT #4 PORT #3 PORT #2 PORT #1 PORT #0 FIFO data Tx FIFO FIFO common 10M/100M/1G data interface Rx FIFO Register set/statistics counter serial CPU bus management interface MII management interface...

  • Page 18: Chapter 2 Pin Functions

    CHAPTER 2 PIN FUNCTIONS (1) Register interface Pin Name Pin No. Function HCS# Input Chip select When this signal is low level, registers within the chip can be accessed. Input Host read/write This is used when the host system accesses the register bus. A read access is executed when high level is input to this pin;...
  • Page 19 CHAPTER 2 PIN FUNCTIONS (2) FIFO interface (1/3) Pin Name Pin No. Function RXFCK Input Receive FIFO bus clock This is the reference clock for RXFCKOUT output. Its maximum frequency is 125 MHz. Give it the same frequency as TXFCK. RXFCKOUT Output Receive FIFO bus clock output...
  • Page 20 CHAPTER 2 PIN FUNCTIONS (2/3) Pin Name Pin No. Function TXFD[127:0] 555, 556, 455, 650, 557, 456, 347, Input Transmit FIFO data bus 230, 651, 558, 457, 348, 231, 106, This provides the 128-bit wide data bus of the transmit FIFO 652, 559, 458, 349, 232, 107, 653, bus interface.
  • Page 21 CHAPTER 2 PIN FUNCTIONS (3/3) Pin Name Pin No. Function RXFDQ[4:0] 519, 414, 301, Output Receive data attributes 180, 51 3 states This shows the attributes of receive data that is on the FIFO bus. On a read access of the receive FIFO, it outputs the attributes of receive data that was output at RXFD[127:0].
  • Page 22 CHAPTER 2 PIN FUNCTIONS (3) Physical layer interface (1/5) Pin Name Pin No. Function TX_CLK[7:0] 649, 644, 325, Input MII transmit clock 534, 281, 498, This transmit clock input is needed in order to output transmit data to the 144, 139 PHY device connected to each port.
  • Page 23 CHAPTER 2 PIN FUNCTIONS (2/5) Pin Name Pin No. Function TXD3[7:0] 395, 502, 601, Output Transmit data (Port 3) 394, 501, 600, This is transmit data output for the PHY device of port 3. 500, 599 In MII mode, the lower 4 bits are used to output a nibble (4 bits) of transmit data in synchronization with the rising edge of TX_CLK3.
  • Page 24 CHAPTER 2 PIN FUNCTIONS (3/5) Pin Name Pin No. Function RX_CLK[7:0]0 339, 334, 78, 200, Input Receive clock 504, 22, 588, 484 This is receive clock input given by a PHY device. Each of RXD7[7:0] to RXD0[7:0], which is the receive data from each port, and RX_DV[7:0], which shows that receive data at RXD is valid, and RX_ER[7:0], which shows that an error occurred in receive data at RXD, are input by port in synchronization with this clock.
  • Page 25 CHAPTER 2 PIN FUNCTIONS (4/5) Pin Name Pin No. Function RXD4[7:0] 628, 199, 318, Input Receive data (Port 4) 429, 71, 198, This is receive data input from the PHY device of port 4. 317, 70 In MII mode, the lower 4 bits are used to input a nibble (4 bits) of receive data on the rising edge of RX_CLK40.
  • Page 26 CHAPTER 2 PIN FUNCTIONS (5/5) Pin Name Pin No. Function CRS[7:0] 337, 546, 76, 197, Input Carrier sense/SIGDET 505, 25, 16, 586 The function of this signal differs depending on the operation mode. (1) In GMII or MII mode This is the carrier sense signal input from the PHY device connected to each port.
  • Page 27 CHAPTER 2 PIN FUNCTIONS (5) Test pins and power supply pins Pin Name Pin No. Function − 756, 752, 748, 745, 741, 737, 735, Power supply (+2.5 V) 731, 727, 724, 720, 716, 714, 710, 706, 703, 699, 695, 693, 689, 685, 682, 678, 674, 474, 461, 454, 451, 434, 431, 427, 420, 407, 400, 396, 393, 380, 373, 128, 119, 114, 105,...

  • Page 28: Chapter 3 Function Description

    CHAPTER 3 FUNCTION DESCRIPTION System Configuration µ PD98433 is an 8-port 10/100/1000 Mbps Ethernet Media Access Controller (MAC) that has a wide range of µ operation modes and features. The PD98433 is a device that was developed for network equipment that requires multiple ports, namely LAN switches and routers.

  • Page 29: Function Blocks

    CHAPTER 3 FUNCTION DESCRIPTION Function Blocks µ As function blocks, the PD98433 has an on-chip MAC module, PCS module, SAL module, STAT module, and FIFO for each port. It also includes a FIFO bus module, MII management module, and register bus module as common modules (see Figure 3-2).

  • Page 30: Pcs Module

    CHAPTER 3 FUNCTION DESCRIPTION 3.2.2 PCS module A PCS module, which is a module for realizing a Physical Coding Sublayer function for connecting to a TBI interface, is connected to a MAC module on the system side. On the network side of a PCS module, a GMII or MII compatible PHY device or a 1000Base-X transceiver can be connected as an external device.

  • Page 31: Register Bus Module

    CHAPTER 3 FUNCTION DESCRIPTION 3.2.8 Register bus module The register bus module provides control registers for performing setup by port or for the entire chip and a register bus for accessing statistics counters for each port. The separate 11-bit wide address bus and bidirectional 32-bit wide data bus are general-purpose buses not dependent on a specific CPU.

  • Page 32: Frame Formats

    CHAPTER 3 FUNCTION DESCRIPTION Frame Formats In an Ethernet network, information is transmitted and received in formats known as packets or frames. A frame or packet used by Ethernet consist of a preamble (PA), start frame delimiter (SFD), destination address (DA), source address (SA), type/length field (TYPE/LEN), data field (DATA), and frame check sequence (FCS) (see Figure 3-3).

  • Page 33: Transmit Operation

    CHAPTER 3 FUNCTION DESCRIPTION Transmit Operation µ PD98433 generates transmit data frames based on data given in the transmit FIFO from a host system. If a collision occurs, it executes a backoff algorithm and retransmits the data in the transmit FIFO. Packet status information such as the number of transmit bytes and the occurrence of errors is set in the TSVREG register after the end of transmission.

  • Page 34: Start Of Packet Transmission

    CHAPTER 3 FUNCTION DESCRIPTION 3.4.2 Start of packet transmission A packet transmit operation to the network side is started by either of the following conditions. • If the amount of data in the transmit FIFO is greater than or equal to a threshold value set in advance •...

  • Page 35: Collisions And Retransmission

    CHAPTER 3 FUNCTION DESCRIPTION 3.4.4 Collisions and retransmission Except in cases in which there are more collisions than the maximum number of collisions set in the RTMAX field of the HDREG register or there are too many collisions in the collision window period set in the COLW field of the µ...
  • Page 36 CHAPTER 3 FUNCTION DESCRIPTION (4) Excessive transmission delay µ If a transmission cannot be started even after 24288-bit time has elapsed since the PD98433 tried to start the transmission, it is considered excessive delay and the transmission is aborted. When excessive delay occurs, the TEDFR bit of the TSVREG register is set to 1.

  • Page 37: Receive Operations

    CHAPTER 3 FUNCTION DESCRIPTION Receive Operations µ PD98433 provides receive data from a receive data stream sent by a PHY device to a host system. The µ PD98433 performs preamble and SFD detection, length field checking, and CRC checking. By setting the MACC3 register, status information can be added to the data stream that is output to the host system from the receive FIFO at the same time that the number of receive bytes, occurrence of errors, and other status information for each receive packet is set in the RSVREG register after an end of receive.

  • Page 38: Address Filtering

    CHAPTER 3 FUNCTION DESCRIPTION 3.5.5 Address filtering µ PD98433 can execute filtering by receive packet destination address and remove receive packets that do not meet conditions. Address filtering conditions are set using the AFR, HT1, HT2, LSA1, and LSA2 registers. Filtering conditions can be set by the address types unicast address, multicast address, and broadcast address.

  • Page 39: Clearing Receive Fifo

    CHAPTER 3 FUNCTION DESCRIPTION 3.5.7 Clearing receive FIFO A host system can clear the contents of receive FIFO by setting the RXFFLH bit of the MACC3 register to 1. If this bit is set in the middle of storing a receive packet in receive FIFO, the packet being received is discarded. If a previous receive packet already is stored in the receive FIFO at that time, that packet also is cleared.

  • Page 40: Receive Status Information

    CHAPTER 3 FUNCTION DESCRIPTION Table 3-1. Receive Status Information Field Function Description RFOV Receive FIFO overflow Indicates that this is a packet for which reception was suspended because it made the receive FIFO overflow. VLAN VLAN frame Indicates that the length/type field of the frame contains the VLAN protocol identifier 8100H. USOP Control frame containing undefined opcode received Indicates that the current frame was recognized as a control frame by the MAC module but that it...

  • Page 41: Full-Duplex Operation

    CHAPTER 3 FUNCTION DESCRIPTION Table 3-2. RBYT Field Field Function Description 31:0 RBYT Receive byte count This shows the total number of bytes in a frame. Full-Duplex Operation µ Each port of the PD98433 is capable of full-duplex operation that transmits and receives packets simultaneously. Setting the FULLD bit of the MACC2 register to 1 enables full-duplex operation.

  • Page 42: System Bus Interface

    CHAPTER 3 FUNCTION DESCRIPTION System Bus Interface µ PD98433 has an on-chip FIFO bus interface and register bus interface for interfacing with a host system. The FIFO bus interface is used to transfer transmit and receive data between on-chip FIFO and a host system. The µ...

  • Page 43: Txfdq Pins And Transmit Data Attributes

    CHAPTER 3 FUNCTION DESCRIPTION TXFPT[2:0] is a signal for specifying the port number of the port that performs a packet transmission. The host system uses this pin to give the port number of the transmit FIFO to be written. TXFD[127:0] is the data bus for writing to transmit FIFO.
  • Page 44 CHAPTER 3 FUNCTION DESCRIPTION By switching TXFPT[2:0] while writing to transmit FIFO, it is possible to continue writing transmit data to the transmit FIFO of another port. In this case, it is possible to write to another port after a rise of TXFCK immediately after switching, but it must be confirmed that the TXFBA signal corresponding to the other port is at high level.
  • Page 45 CHAPTER 3 FUNCTION DESCRIPTION (2) Receive FIFO bus interface operations Figure 3-8. FIFO Interface Read Timing RXFCKOUT RXFEN# RXFA RXFDQ[4] RXFDQ[3] RXFDQ[2] RXFDQ[1] RXFDQ[0] Port number RXFPT[2:0] RXFD[127:0] 2nd word 3rd word n− 1 th word n th word RXPAR 1st word 128 bits PASS SKIP...

  • Page 46: Rxfdq Pins And Receive Data Attributes

    CHAPTER 3 FUNCTION DESCRIPTION Table 3-4. RXFDQ Pins and Receive Data Attributes RXFDQ Meaning Valid Data Big Endian Little Endian Idle None None Start of data FEDCBA9876543210 FEDCBA9876543210 Middle of data FEDCBA9876543210 FEDCBA9876543210 Reserved None None Status information (Beginning) FEDCBA9876543210 FEDCBA9876543210 Status information (End) FEDCBA9876543210...
  • Page 47 CHAPTER 3 FUNCTION DESCRIPTION µ The order of ports when performing receive data transfer is determined in advance in the PD98433. The sequence Port 0 → Port 1 → Port 2 → ... Port 7 → Port 0 →... is repeated. However, on a shift to the next port, if a complete packet of receive data has not been stored in that port and the threshold value set in the THRX field of the RFIC3 register is not exceeded, the port is skipped and its turn goes to the next port.
  • Page 48 CHAPTER 3 FUNCTION DESCRIPTION (b) SKIP signal µ The port number of the receive FIFO whose data is read via the FIFO bus is designated by the PD98433. However, if a SKIP signal is input when the reading of receive FIFO is enabled and the RXFA signal is high level or in the middle of reading receive data using burst transfer, the host system can read a port other µ...
  • Page 49 CHAPTER 3 FUNCTION DESCRIPTION Next, Figure 3-11 shows an example of the timing when switching ports due to a SKIP signal while reading. µ In this case, the port switches two clocks of RXFCKOUT after the SKIP signal is detected. The PD98433 outputs valid receive data for two clocks until the port switches.
  • Page 50 CHAPTER 3 FUNCTION DESCRIPTION Figure 3-11. Timing of Read Port Switch Due to SKIP Signal (During Read) (2/2) (b) Skipped port and next port are the same RXFCKOUT RXFEN# RXFA RXFDQ[4] RXFDQ[3] RXFDQ[2] RXFDQ[1] RXFDQ[0] RXFPT[2:0] Port number M Port number M 2nd word n−...

  • Page 51: Register Bus Interface

    CHAPTER 3 FUNCTION DESCRIPTION 3.7.2 Register bus interface µ PD98433 provides a register bus interface for accessing control registers, statistics counters, and other on- µ chip registers of the PD98433. The register bus interface consists of a 32-bit wide bidirectional data bus, 11-bit width address bus, and control signals (HCS# signal, HRW signal, and HACK# signal).
  • Page 52 CHAPTER 3 FUNCTION DESCRIPTION (3) Interrupt servicing µ If an interrupt source generates, the PD98433 makes the INT# signal low level and notifies the host system. The following are sources of interrupts. • Transmit packet status information shown in the TSVREG register •...

  • Page 53: Network Interface

    CHAPTER 3 FUNCTION DESCRIPTION Network Interface µ PD98433 has an on-chip GMII (Gigabit Media Independent Interface), MII (Media Independent Interface) and TBI (Ten Bit Interface) compliant with IEEE802.3 as network side interfaces. By setting the GMII/MII bit of the PYTBIC register and the IFMOD field of the MACC2 register, it is possible to select the interface to use in each port.

  • Page 54: Mii Management Interface

    CHAPTER 3 FUNCTION DESCRIPTION 3.8.4 MII management interface µ PD98433 provides an MII management interface, which is a 2-wire serial interface for access between PHY devices using MII management interface frames. This interface is used to access registers of an external PHY device or internal PCS (TBI) module.
  • Page 55 CHAPTER 3 FUNCTION DESCRIPTION (2) MII management frame data Figure 3-13 shows the MII management frame structure. Figure 3-13. MII Management Frame Structure (a) Write MDIO (Output) (Data) (Preamble) = all 1 (Start bit) = 01 (Turnaround) = 10 (Operation) = 01 PHYAD REGAD (b) Read or scan...

  • Page 56: Pd98433 Connection Of Mii Output Signal Pins

    CHAPTER 3 FUNCTION DESCRIPTION (3) Access procedures MII management frames are transmitted and received as follows. First, check the BUSY bit of the MIND register to check whether or not there is a current MII management access. If the BUSY bit is on, wait until it is turned off. Next, set the target external PHY device address and the address of the register in the PHY in the PYAD field and RGAD field of the MADR register, respectively.

  • Page 57: Flow Control

    CHAPTER 3 FUNCTION DESCRIPTION Flow Control µ PD98433 realizes flow control by performing the pause control frame processing in IEEE 802.3 Chapter 31. The purpose of flow control is to reduce the frequency of transmitting packets that were transmitted from another terminal that is connected point-to-point in full-duplex operation.

  • Page 58: Pause Control Frame Transmission

    CHAPTER 3 FUNCTION DESCRIPTION 3.9.3 Pause control frame transmission µ PD98433 generates and transmits pause control frames according to the status of receive FIFO use and designation by an external pin. (1) Pause control frame issuance by FIFO threshold value specification µ...
  • Page 59 CHAPTER 3 FUNCTION DESCRIPTION (2) Pause retransmission interval timer µ PD98433 sets the initial value of the pause retransmission interval counter according to the setting of the IPTIME field of the ICFPT register. The pause retransmission interval timer starts a countdown when a pause control frame is sent, and if the amount of data stored in receive FIFO when it reaches 0 exceeds the threshold value set in the RFWMH field of the RFIC1 register, it automatically transmits a pause control frame again, prompting an extension of the pause period.
  • Page 60 CHAPTER 3 FUNCTION DESCRIPTION Figure 3-16. Reissuance of Pause Control Frame by Pause Retransmission Interval Timer (2/2) (b) Reissuance of pause control frame when pause period elapses RFWMH RFWML IPTIME : Pause frame transmitted Time (c) Issuance of zero pause control frame during pause period RFWMH RFWML IPTIME...

  • Page 61: Back Pressure

    CHAPTER 3 FUNCTION DESCRIPTION 3.10 Back Pressure µ PD98433 has an on-chip back pressure function. This function, which is valid only for half-duplex operation, is enabled if the amount of data in receive FIFO exceeds the threshold level set in the RFWMH field of the RFIC1 register when the BACKPE bit of the MACC3 register is 1.

  • Page 62: Loopback

    CHAPTER 3 FUNCTION DESCRIPTION 3.13 Loopback Setting the LPBK bit of the MACC1 register to 1 loops back a GMII/MII transmit data stream internally as a GMII/MII receive data stream. TXCLKn is connected to RXCLKn internally. COLn and CRSn are ignored. When used in loopback, the FULLD bit of the MACC2 register must be set to 1 to set full-duplex operation mode.

  • Page 63: Software Reset

    CHAPTER 3 FUNCTION DESCRIPTION 3.15 Software Reset µ PD98433 requires software resets at the following times. • After switching TBI, GMII, and MII modes • After manually changing full-duplex and half-duplex operation • After switching normal operation and loopback mode µ...

  • Page 64: Turning Power On

    CHAPTER 3 FUNCTION DESCRIPTION 3.16 Turning Power ON µ PD98433 has two types of power supply pins: 2.5 V power supply pins for internal units (VDD), 3.3 V power supply pins for physical layer interface I/O buffers (VDDQ). This section explains the sequence when power is turned ON. Figure 3-17.

  • Page 65: Chapter 4 Register Description

    CHAPTER 4 REGISTER DESCRIPTION Control Register Map (1) Port control register map (1/2) Register Address Name Function Default HA[7:0] MACC1 MAC configuration register 1 8000 0000H MACC2 MAC configuration register 2 0000 7201H IPGIFG IPG/IFG register 4060 5060H HDREG Half-duplex configuration register 00A0 F037H LMAX Maximum frame length configuration register...
  • Page 66 CHAPTER 4 REGISTER DESCRIPTION (2/2) Register Address Name Function Default HA[7:0] FSVREG FIFO status register 0000 0000H − − − 2C to 2FH Reserved RFIC1 Receive FIFO configuration register 1 17FF 0000H RFIC2 Receive FIFO configuration register 2 0000 000FH RFIC3 Receive FIFO configuration register 3 1FFF 1FFFH...

  • Page 67: Port Configuration Registers

    CHAPTER 4 REGISTER DESCRIPTION Port Configuration Registers Port configuration registers are registers for defining the operation of each port or for checking the status of each port. In order to access the registers of each port, the port number is input in HA[10:8] of the address bus HA[10:0] and the address of the register is input in HA[7:0].
  • Page 68 CHAPTER 4 REGISTER DESCRIPTION (2/2) Name Function Default − − Reserved Write 0. Receive enable Setting this bit enables frame reception from PHY. Setting it to 0 stops frame reception. − − Reserved Write 0. Transmit enable Setting this bit enables the MAC to transmit frames from a system. Setting it to 0 stops frame transmission.
  • Page 69 CHAPTER 4 REGISTER DESCRIPTION MACC2 - MAC configuration register 2 (Register address HA[7:0] = 01H) R/W Reserved PRELN Reserved IFMOD Reserved HUGEN LENCK PADEN CRCEN FULLD Reserved Name Function Default − − 31:16 Reserved Write 0. 15:12 PRELN Preamble length Specifies the length of the preamble of a packet in bytes.
  • Page 70 CHAPTER 4 REGISTER DESCRIPTION IPGIFG - IFG/IPG register (Register address HA[7:0] = 02H) R/W IPGR1 IPGR2 Reserved Reserved MINIFG IPGT Reserved Name Function Default − − Reserved Write 0. 30:24 IPGR1 NON-BACK-TO-BACK INTER-PACKET-GAP PART 1 This field shows the carrierSense period within the inter-packet gap when transmitting.
  • Page 71 CHAPTER 4 REGISTER DESCRIPTION HDREG - Half-duplex configuration register (Register address HA[7:0] = 03H) R/W Reserved ABEXT ABEXE BKPNB NBOF Reserved RTMAX Reserved COLW Name Function Default − − 31:24 Reserved Write 0. 23:20 ABEXT ALTERNATE BINARY EXPONENTIAL BACKOFF TRUNCATION When the ALTERNATE BINARY EXPONENTIAL BACKOFF ENABLE bit is set, backoff time is calculated using this field.
  • Page 72 CHAPTER 4 REGISTER DESCRIPTION LMAX - Maximum frame length configuration register (Register address HA[7:0] = 04H) R/W Reserved LMAX Name Function Default − − 31:16 Reserved Write 0. 15:0 LMAX Maximum frame length 0600H This field sets a limit on the maximum frame length in both the transmit and receive directions.
  • Page 73 CHAPTER 4 REGISTER DESCRIPTION MIIC - MII serial management configuration register (Register address HA[7:0] = 08H) R/W SRST Reserved Reserved CLKS PRESUP Reserved Name Function Default SRST MII management module reset Setting this bit resets the MII management module. Clearing this bit makes it possible to use MII management module in order to execute a serial management read/write cycle.
  • Page 74 CHAPTER 4 REGISTER DESCRIPTION MCMD - MII serial management command register (Register address HA[7:0] = 09H) R/W Reserved Reserved SCAN RSTAT Name Function Default − − 31:2 Reserved Write 0. SCAN Scan cycle Setting this bit executes a read cycle continuously. This can be used, for example, to monitor link failure.
  • Page 75 CHAPTER 4 REGISTER DESCRIPTION MWTD - MII serial management write data register (Register address HA[7:0] = 0BH) R/W Reserved MCTL Name Function Default − − 31:16 Reserved 15:0 MCTL MII write data 0000H Performing a write to this register executes an MII management write cycle. The PHY address and register address of the MII management frame are set using the value set in the MADR register (0AH) and write data is set using the value set in MWTD (08H).
  • Page 76 CHAPTER 4 REGISTER DESCRIPTION MIND - MII serial management indicator (Register address HA[7:0] = 0DH) Read only Reserved Reserved NVAL SCAN BUSY Name Function Default − − 31:3 Reserved Write 0. NVAL MSTA register invalid If 1 is returned in this bit, it shows that the MII management read cycle did not complete or the read data is not yet valid.
  • Page 77 CHAPTER 4 REGISTER DESCRIPTION LSA1 - Station address register 1 (Register address HA[7:0] = 10H) R/W STA1 STA2 STA3 STA4 Name Function Default 31:24 STA1 Station address, 1st octet This field contains a station address SA[7:0]. SA[7:0] is written in 31:24. 23:16 STA2 Station address, 2nd octet...
  • Page 78 CHAPTER 4 REGISTER DESCRIPTION CAR1 - CARRY register 1 (Register address HA[7:0] = 1CH) R/W C1R64 C1R127 C1R255 C1R511 C1R1K Reserved C1RBY C1RMAX C1REXD C1RPK C1RFC C1RMC C1RBC C1RXC C1RXP C1RXU C1RAL C1RFL C1RCD C1RCS C1RUN C1ROV C1RFR C1RJB C1RDR CAR1 shows that statistics counters overflowed.
  • Page 79 CHAPTER 4 REGISTER DESCRIPTION CAR2 - Carry register 2 (Register address HA[7:0] = 1DH) R/W C2T64 C2T127 C2T255 C2T511 C2T1K C2TMAX Reserved C2TPAR C2TJB C2TFC C2TCF C2TOV C2TEXD C2TUN C2TFG C2TBY C2TPK C2TMC C2TBC C2TPF C2TDF C2TED C2TSC C2TMA C2TLC C2TXC C2TNC C2TDP Reserved Name...
  • Page 80 CHAPTER 4 REGISTER DESCRIPTION CAM1 - Carry mask register (Register address HA[7:0] = 1EH) R/W M1R64 M1R127 M1R255 M1R511 M1R1K Reserved M1RBY M1RMAX M1REXD M1RPK M1RFC M1RMC M1RXC M1RXP M1RXU M1RAL M1RFL M1RCD M1RCS M1RUN M1ROV M1RFR MC1RJB M1RDR MC1RBC CAM1 masks INT# signals that occur when bits within the CAR1 register are set to 1.
  • Page 81 CHAPTER 4 REGISTER DESCRIPTION CAM2 - Carry mask register 2 (Register address HA[7:0] = 1FH) R/W M2T64 M2T127 M2T255 M2T511 M2T1K Reserved M2TPAR M2TJB M2TFC M2TCF M2TOV M2TMAX M2TEXD M2TUN M2TFG M2TBY M2TPK M2TMC M2TBC M2TPF M2TDF M2TED M2TSC M2TMA M2TLC M2TXC M2TNC M2TDP Reserved Name...
  • Page 82 CHAPTER 4 REGISTER DESCRIPTION STLC - Statistics counter configuration register (Register address HA[7:0] = 20H) R/W Reserved Reserved Reserved Name Function Default − − 31:3 Reserved Write 0. Statistics counter read reset If set to 1, statistics counters are reset on a read. −...
  • Page 83 CHAPTER 4 REGISTER DESCRIPTION HT1 - HASH table 1 (Register address HA[7:0] = 22H) R/W HT1[31:16] HT1[15:0] Name Function Default 31:0 HASH table 1 0000 0000H This is the higher table of the hash tables used in address filtering of multicast packets.
  • Page 84 CHAPTER 4 REGISTER DESCRIPTION ICFPT - Internal pause timer register (Register address HA[7:0] = 25H) R/W Reserved IPTIME[15:0] Name Function Default − − 31:16 Reserved Write 0. 15:0 IPTIME Pause retransmission interval timer 0000H This register sets the initial value of the pause retransmission interval timer in pause_quanta units (512-bit time).
  • Page 85 CHAPTER 4 REGISTER DESCRIPTION MACC3 - MAC configuration register 3 (Register address HA[7:0] = 26H) R/W Reserved Reserved APSE APSS BACKPE TXFFLH RXFFLH Reserved FLWCNT Name Function Default − − 31:7 Reserved Write 0. APSE Status information addition (end of packet data) When this bit is 1, status information is added at the end of a packet.
  • Page 86 CHAPTER 4 REGISTER DESCRIPTION TIMR - Transmit interrupt mask register (Register address HA[7:0] = 27H) R/W Reserved ITPER ITFOV ITFUN ITWMH ITVLTF IBPA ITPCF ITCF ITURUN ITGNT ITLCOL ITMXCO ITEDFR ITDFR ITBRO ITMUL ITDONE ITFLOR ITFLER ITCRCE TIMR masks the occurrence of INT# signals by cause. Setting each bit to 1 cancels masking. (1/2) Name Function...
  • Page 87 CHAPTER 4 REGISTER DESCRIPTION (2/2) Name Function Default ITFLOR Length field check If 0, the interrupt of the corresponding bit of the TSVREG register is masked. ITFLER Data length mismatch If 0, the interrupt of the corresponding bit of the TSVREG register is masked. ITCRCE Transmit CRC error If 0, the interrupt of the corresponding bit of the TSVREG register is masked.
  • Page 88 CHAPTER 4 REGISTER DESCRIPTION (2/2) Name Function Default RLOR Length field check If 0, the interrupt of the corresponding bit of the RSVREG register is masked. RLER Data length mismatch If 0, the interrupt of the corresponding bit of the RSVREG register is masked. RCRCE CRC error If 0, the interrupt of the corresponding bit of the RSVREG register is masked.
  • Page 89 CHAPTER 4 REGISTER DESCRIPTION TSVREG - Transmit status register (Register address HA[7:0] = 29H) R/W Reserved TVLTF TPCF TURUN TGNT TLCOL TMXCO TEDFR TDFR TBRO TMUL TDONE TFLOR TFLER TCRCE This register shows the interrupt source when the INT# signal is low level due to the status of a transmit packet (except Reserved).
  • Page 90 CHAPTER 4 REGISTER DESCRIPTION (2/2) Name Function Default TBRO Broadcast packet transmitted If 1, this shows that a broadcast packet was transmitted. If the transmit is aborted, it does not become 1 (this occurs if a transmit succeeds). TMUL Multicast packet transmitted If 1, this shows that a multicast packet was transmitted.
  • Page 91 CHAPTER 4 REGISTER DESCRIPTION RSVREG - Receive status register (Register address HA[7:0] - 2AH) R/W Reserved VLAN USOP RPCF RCFR DBNB RBRO RMUL RLOR RLER RCRCE RFCA REPS RPPD Reserved This register shows the interrupt source when the INT# signal is low level due to the status of a receive packet (except Reserved).
  • Page 92 CHAPTER 4 REGISTER DESCRIPTION (2/2) Name Function Default RLER Data length mismatch If 1, this shows that the value of the length field does not match the length of the data field in a received packet. If the LENCK bit of the MACC2 register is 0, this bit does not become 1.
  • Page 93 CHAPTER 4 REGISTER DESCRIPTION FSVREG - FIFO status register (Register address HA[7:0] = 2BH) R/W Reserved TPER Reserved TFOV TFUN TWMH Reserved RFOV RWMH RWML This register shows the interrupt source when the INT# signal is low level due to each status (except Reserved). When the interrupt source of each bit occurs, the corresponding bit is set to 1 and the INT# signal is made low level.
  • Page 94 CHAPTER 4 REGISTER DESCRIPTION RFIC1 - Receive FIFO configuration register 1 (Register address HA[7:0] = 30H) R/W Reserved RFWMH Reserved RFWML Name Function Default − − 31:29 Reserved Write 0. 28:16 RFWMH Pause frame transmission level 17FFH When the transmit flow control function is enabled, a pause frame that has the pause timer value that is set in the CFPT register is transmitted automatically if the amount of data in receive FIFO exceeds this value.
  • Page 95 CHAPTER 4 REGISTER DESCRIPTION RFIC2 - Receive FIFO configuration register 2 (Register address HA[7:0] = 31H) R/W Reserved Reserved DDNB SIFT DCRCE FCRX Name Function Default − − 31:4 Reserved Write 0. DDNB Dribble nibble discard If this bit is 1, dribble nibble packets are discarded. SIFT Short packet discard If this bit is 1, packets that are less than 64 bytes are discarded.
  • Page 96 CHAPTER 4 REGISTER DESCRIPTION RFIC3 - Receive FIFO configuration register 3 (Register address HA[7:0] = 32H) R/W Reserved THRX Reserved RXETH Name Function Default − − 31:29 Reserved Write 0. 28:16 THRX Receive completed threshold value 1FFFH If receive data in receive FIFO exceeds this THRX threshold value, the RXFA signal is asserted.
  • Page 97 CHAPTER 4 REGISTER DESCRIPTION TFIC1 - Transmit FIFO configuration register 1 (Register address HA[7:0] = 33H) R/W Reserved TFWMH Reserved TFDWL Name Function Default − − 31:29 Reserved Write 0. 28:16 TFWMH Transmit full level 1200H If the amount of data in transmit FIFO is less than or equal to this value, the µ...
  • Page 98 CHAPTER 4 REGISTER DESCRIPTION UFCR - User field configuration register (Register address HA[7:0] = 35H) R/W UFCR[31:16] UFCR[15:0] Name Function Default 31:0 UFCR User field 0000 0000H The value written in this register is output in RXFD[95:64] on output of status and RBYT fields.

  • Page 99: Global Registers

    CHAPTER 4 REGISTER DESCRIPTION Global Registers Global registers are registers that are used to make settings and check status for all ports. When accessing a global register, only HA[7:0] of the address bus HA[10:0] is valid and HA[10:8] is ignored. STIR - Status information register (Register address HA[7:0] = FBH) Read only P7TS P7RS...
  • Page 100 CHAPTER 4 REGISTER DESCRIPTION (2/2) Name Function Default P4RS Port 4 RSVREG status When any bit in the RSVREG register of port 4 is set to 1, this bit is set to 1. P4FS Port 4 FSVREG status When any bit in the FSVREG register of port 4 is set to 1, this bit is set to 1. P4CA Port 4 CAR status When any bit in the CAR1 or CAR2 register of port 4 is set to 1, this bit is set...
  • Page 101 CHAPTER 4 REGISTER DESCRIPTION MISCR - FIFO configuration register (Register address HA[7:0] = FCH) R/W Reserved PSEL Reserved BUSMODE Reserved INTEN Reserved SRRC Name Function Default − − 31:27 Reserved Write 0. BUSMODE FIFO I/F little endian/big endian selection If this bit is 0, it specifies little endian. If this bit is 1, it specifies big endian.
  • Page 102 CHAPTER 4 REGISTER DESCRIPTION CLKCHK – Clock Check register (Register address HA[7:0] = FDH) R/W Reserved TXFCK RXFCK GTX_REF_CLK TX_CLK7 TX_CLK6 TX_CLK5 TX_CLK4 TX_CLK3 TX_CLK2 TX_CLK1 TX_CLK0 RX_CLK71 RX_CLK61 RX_CLK51 RX_CLK41 RX_CLK31 RX_CLK21 RX_CLK11 RX_CLK01 RX_CLK70 RX_CLK60 RX_CLK50 RX_CLK40 RX_CLK30 RX_CLK20 RX_CLK10 RX_CLK00 This register shows the input status of each clock.
  • Page 103 CHAPTER 4 REGISTER DESCRIPTION POWD - Power down control register (Register address HA[7:0] = FFH) R/W Reserved Reserved Name Function Default − − 31:8 Reserved Write 0. Port 7 power down This sets power down mode. Making this bit 1 cuts clock supply to the port block in the device.

  • Page 104: Pcs Configuration Registers

    CHAPTER 4 REGISTER DESCRIPTION PCS Configuration Registers The PCS configuration registers are a set of 16-bit wide registers that can be accessed via MII serial management. PYCNT - Control register (Register address RGAD[4:0] = 00H) R/W Reserved Reserved Reserved Reserved Name Function Default...
  • Page 105 CHAPTER 4 REGISTER DESCRIPTION PYSTS - Status register (Register address RGAD[4:0] = 01H) Read only Reserved NPRE Reserved Reserved Name Function Default − − 15:9 Reserved Write 0. Extension status This bit shows that register 15 (extension status) contains further PHY status information.
  • Page 106 CHAPTER 4 REGISTER DESCRIPTION PYANA - Auto-Negotiation Advertisement register (Register address RGAD[4:0] = 04H) R/W Reserved Reserved Reserved Name Function Default Next page If this bit is 1, it requests transmission of the next page or reports to the link partner that it has the ability to swap the next page.

  • Page 107: Pause Order Of Precedence Resolution Table

    CHAPTER 4 REGISTER DESCRIPTION Table 4-1. Pause Order of Precedence Resolution Table Local Device Link Partner Local Resolution Link Partner Resolution PAUSE ASM_DIR PAUSE ASM_DIR Pause transmit disabled Pause transmit disabled Pause receive disabled Pause receive disabled Pause transmit disabled Pause transmit disabled Pause receive disabled Pause receive disabled...
  • Page 108 CHAPTER 4 REGISTER DESCRIPTION PYANBP - Auto-Negotiation Link Partner Base Page Ability register (Register address RGAD[4:0] = 05H) Read only Reserved Reserved Reserved Name Function Default Next page A link partner asserts this bit to perform a next page transmit or to show its ability to receive the next page.
  • Page 109 CHAPTER 4 REGISTER DESCRIPTION PYANEX - Auto-Negotiation extension register (Register address RGAD[4:0] = 06H) Read only Reserved Reserved Name Function Default − − 15:3 Reserved Write 0. Next page available If this bit is 1, it shows that the local device supports the next page function. This bit is fixed to 1.
  • Page 110 CHAPTER 4 REGISTER DESCRIPTION PYANLPN - Auto-Negotiation Link Partner Ability Next Page register (Register address RGAD[4:0] = 08H) Read only MSGUFC Reserved Name Function Default Next page If this bit is 1, a link partner set this bit to show that there continues to be an additional next page.
  • Page 111 CHAPTER 4 REGISTER DESCRIPTION PYEX - Extension status register (Register address RGAD[4:0] = 0FH) Read only Reserved Name Function Default 1000BASE-X full-duplex This bit is fixed to 1. 1: Shows that PHY can operate in 1000BASE-X full-duplex mode. 0: Shows that PHY cannot operate in 1000BASE-X full-duplex mode. 1000BASE-X half-duplex This bit is fixed to 0.
  • Page 112 CHAPTER 4 REGISTER DESCRIPTION PYJTR - Jitter diagnosis register (Register address RGAD[4:0] = 10H) R/W Reserved Name Function Default Jitter diagnosis enable If this bit is 1, the function that transmits jitter test patterns defined in IEEE 802.3 Annex 36A can be used. Clear this bit to make it possible to use normal transmit operations.
  • Page 113 CHAPTER 4 REGISTER DESCRIPTION PYTBIC - TBI control register (Register address RGAD[4:0] = 11H) R/W Reserved Reserved RCKSEL GMII/MII Reserved ERAP CDET Reserved Name Function Default Software reset This bit resets the function module in the TBI. Clear this bit to perform normal operations.

  • Page 114: Chapter 5 Statistics Counters

    CHAPTER 5 STATISTICS COUNTERS Statistics counter map (1/2) Register Address Name Function Default HA[7:0] 64-byte frame receive counter 0000 0000H R127 65- to 127-byte frame receive counter 0000 0000H R255 128- to 255-byte frame receive counter 0000 0000H R511 256- to 511-byte frame receive counter 0000 0000H 512- to 1023-byte frame receive counter 0000 0000H...
  • Page 115 CHAPTER 5 STATISTICS COUNTERS (2/2) Register Address Name Function Default HA[7:0] TMCA Multicast packet transmit counter 0000 0000H TBCA Broadcast packet transmit counter 0000 0000H TXPF Pause control frame transmit counter 0000 0000H TDFR Transmit delay counter 0000 0000H TEDF Transmit excessive delay counter 0000 0000H TSCL...
  • Page 116 CHAPTER 5 STATISTICS COUNTERS R64 - 64-byte frame receive counter (Register address HA[7:0] = 80H) Read/Write R64(31:16) R64(15:0) R64 counts the number of 64-byte long receive frames. Receive frames include normal receive frames and receive frames that have errors. (Preamble and SFD are excluded from the frame length, but the FCS field is included.) R127 - 65- to 127-byte frame receive counter (Register address HA[7:0] = 81H) Read/Write R127(31:16) R127(15:0)
  • Page 117 CHAPTER 5 STATISTICS COUNTERS R1K - 512- to 1023-byte frame receive counter (Register address HA[7:0] = 84H) Read/Write R1K(31:16) R1K(15:0) R1K counts the number of 512-byte to 1023-byte long receive frames. Receive frames include normal receive frames and receive frames that have errors. (Preamble and SFD are excluded from the frame length, but the FCS field is included.) RMAX - 1024- to 1518-byte frame receive counter (Register address HA[7:0] = 85H) Read/Write RMAX(31:16)
  • Page 118 CHAPTER 5 STATISTICS COUNTERS RPKT - Packet receive counter (Register address HA[7:0] = 88H) Read/Write RPKT(31:16) RPKT(15:0) RPKT counts the number of packets received. This counter also counts incorrect packets. In addition, it counts all unicast, multicast, and broadcast packets. RFCS - FCS error receive counter (Register address HA[7:0] = 89H) Read/Write RFCS(31:16) RFCS(15:0)
  • Page 119 CHAPTER 5 STATISTICS COUNTERS RXCF - Control frame receive counter (Register address HA[7:0] = 8CH) Read/Write RXCF(31:16) RXCF(15:0) RXCF counts the number of MAC control frames (length/type field is 8808H) received. Unsupported commands except for pause frame are included. RXPF - Pause frame receive counter (Register address HA[7:0] = 8DH) Read/Write RXPF(31:16) RXPF(15:0) RXPF counts the number of valid pause MAC control frames (valid destination address, length/type field is 8808H,...
  • Page 120 CHAPTER 5 STATISTICS COUNTERS RFLR - Data length mismatch receive counter (Register address HA[7:0] = 90H) Read/Write RFLR(31:16) RFLR(15:0) RFLR counts the number of cases in which the data length of frames actually received does not match the length field value. Invalid IEEE802.3 length field values (non-VLAN: except 46-1500 byte, VLAN: except 42-1500 byte) are not counted.
  • Page 121 CHAPTER 5 STATISTICS COUNTERS ROVR - Oversize packet receive counter (Register address HA[7:0] = 94H) Read/Write ROVR(31:16) ROVR(15:0) When HUGEN of the MACC2 register is cleared to 0, this counter counts the number of frames that exceeds the maximum frame length set to the LMAX register. It also counts receive frames that contain an error. When HUGEN of the MACC2 register is set to 1, this counter counts nothing.
  • Page 122 CHAPTER 5 STATISTICS COUNTERS T127 - 65- to 127-byte frame transmit counter (Register address HA[7:0] = A1H) Read/Write T127(31:16) T127(15:0) T127 counts the number of 65-byte to 127-byte long transmit frames. Transmit frames include normal transmit frames and transmit frames that have errors. (Preamble and SFD are excluded from the frame length, but the FCS field is included.) T255 - 128- to 255-byte frame transmit counter (Register address HA[7:0] = A2H) Read/Write T255(31:16)
  • Page 123 CHAPTER 5 STATISTICS COUNTERS TMAX - 1024- to 1518-byte frame transmit counter (Register address HA[7:0] = A5H) Read/Write TMAX(31:16) TMAX(15:0) TMAX counts the number of 1024-byte to 1518-byte long transmit frames. Transmit frames include normal transmit frames and transmit frames that have errors. (Preamble and SFD are excluded from the frame length, but the FCS field is included.) TEXD - 1519- to LMAX frame transmit counter (Register address HA[7:0] = A6H) Read/Write TEXD(31:16)
  • Page 124 CHAPTER 5 STATISTICS COUNTERS TPKT - Packet transmit counter (Register address HA[7:0] = A8H) Read/Write TPKT(31:16) TPKT(15:0) TPKT is counted for every packet transmission. It includes packets in which errors occur, all unicast packets, all multicast packets, and broadcast packets. TMCA - Multicast packet transmit counter (Register address HA[7:0] = A9H) Read/Write TMCA(31:16) TMCA(15:0)
  • Page 125 CHAPTER 5 STATISTICS COUNTERS TDFR - Transmit delay counter (Register address HA[7:0] = ACH) Read/Write TDFR(31:16) TDFR(15:0) TDFR is counted when a transmit delay occurs due to carrier detection when trying to start transmission. This counter is not counted if a collision occurs during a transmit started after a delay occurs. This counter is counted only when the transmit succeeds.
  • Page 126 CHAPTER 5 STATISTICS COUNTERS TLCL - Late collisions counter (Register address HA[7:0] = B0H) Read/Write TLCL(31:16) TLCL(15:0) TLCL is counted when a late collision occurs on transfer. TXCL - Excessive collisions counter (Register address HA[7:0] = B1H) Read/Write TXCL(31:16) TXCL(15:0) TXCL is counted when more collisions than the RTMAX field of the HDREG register occur during transmission and transmission is aborted.
  • Page 127 CHAPTER 5 STATISTICS COUNTERS TJBR - Jabber frame transmit counter (Register address HA[7:0] = B5H) Read/Write TJBR(31:16) TJBR(15:0) TJBR counts when a packet that exceeds 1518 octets and has an incorrect FCS is transmitted. TFCS - FCS error packet transmit counter (Register address HA[7:0] = B6H) Read/Write TFCS(31:16) TFCS(15:0) TFCS counts when a valid sized packet (non-VLAN: 64-1518 byte, VLAN: 64-1522 byte) that has an incorrect FCS...
  • Page 128 CHAPTER 5 STATISTICS COUNTERS TUND - Short packet transmit counter (Register address HA[7:0] = B9H) Read/Write TUND(31:16) TUND(15:0) TUND counts the number of frames of less than 64 bytes that have a correct FCS. TFRG - Error short packet transmit counter (Register address HA[7:0] = BAH) Read/Write TFRG(31:16) TFRG(15:0) TFRG counts the number of frames of less than 64 bytes that have an incorrect FCS.

  • Page 129: Chapter 6 Jtag Boundary Scan

    CHAPTER 6 JTAG BOUNDARY SCAN µ PD98433 has a JTAG boundary scan circuit. Features • Conforms to IEEE1149.1 JTAG Boundary Scan Standard. • Three registers dedicated to boundary scan • Instruction register • Bypass register • Boundary scan register • Three instructions supported •...

  • Page 130: Internal Configuration Of Boundary Scan Circuit

    CHAPTER 6 JTAG BOUNDARY SCAN Internal Configuration of Boundary Scan Circuit µ Figure 6-1 shows the block diagram of the internal JTAG boundary scan circuit of the PD98433. Figure 6-1. Block Diagram of Boundary Scan Circuit Boundary scan register Bypass register Output buffer Instruction decoder Instruction register...

  • Page 131: Pin Function

    CHAPTER 6 JTAG BOUNDARY SCAN Pin Function 6.3.1 TCK (JTAG Test Clock) pin The TCK pin is used to supply a clock signal to the JTAG boundary scan circuit (such as the bypass register, instruction register, and TAP controller. This clock signal is isolated so as not to be supplied to the other internal µ...

  • Page 132: Operation Description

    CHAPTER 6 JTAG BOUNDARY SCAN Operation Description 6.4.1 TAP controller The TAP controller is a circuit having 16 states synchronized with changes of the TMS and TCK pins. Its operation is specified by IEEE Standard 1149.1. 6.4.2 TAP controller state Figure 6-2 shows the state transition of the TAP controller.
  • Page 133 CHAPTER 6 JTAG BOUNDARY SCAN Figure 6-3. Operation Timing in Controller State Controller state Enters state Starts in state Starts in state at falling edge of TCK pin at rising edge of TCK pin (1) Test-Logic-Reset µ The JTAG boundary scan circuit does not affect the normal operation of the PD98433 in this controller status.
  • Page 134 CHAPTER 6 JTAG BOUNDARY SCAN (4) Select-IR-Scan This is a temporary boundary scan state. The boundary scan register and bypass register selected by the current instruction hold the previous state. If the TMS pin signal is held low at the rising edge of the TCK pin signal while the TAP controller is in this state, the controller enters the Capture-IR state, and scan sequence to the selected registers is started.
  • Page 135 CHAPTER 6 JTAG BOUNDARY SCAN (9) Exit2-DR This is a temporary controller state. If the TMS pin signal is held high at the rising edge of the TCK pin signal with the TAP controller in this state, the controller enters the Update-DR state. This ends the scan process. If the TMS pin signal is held low at the rising edge of the TCK pin signal, the TAP controller enters the Shift-DR state.
  • Page 136 CHAPTER 6 JTAG BOUNDARY SCAN (13) Exit1-IR This is a temporary controller state. If the TMS pin signal is held high at the rising edge of the TCK pin signal, the TAP controller enters the Update-IR state. This ends the scan process. If the TMS pin signal is held low at the rising edge of the TCK pin signal, the TAP controller enters the Pause- IR state.

  • Page 137: Tap Controller Operation

    CHAPTER 6 JTAG BOUNDARY SCAN TAP Controller Operation The TAP controller operates as follows. The state of the controller is changed by either of (1) and (2) below. (1) Rising edge of TCK pin signal (2) TRST# pin input The TAP controller generates signals that control the operations of the bypass register, boundary scan register, and instruction register defined by the IEEE1149.1 JTAG Boundary Scan Standard (refer to Figures 6-4 and 6-5).
  • Page 138 CHAPTER 6 JTAG BOUNDARY SCAN Figure 6-4. Operation of Test Logic (Instruction Scan) TCK pin signal TMS pin signal Controller state TDI pin signal Input data to IR IR shift register Parallel output of IR Bypass New instruction Note Input data to TDR TDR shift register Parallel output of TDR Old data...
  • Page 139 CHAPTER 6 JTAG BOUNDARY SCAN Figure 6-5. Operation of Test Logic (Data Scan) TCK pin signal TMS pin signal Controller state TDI pin signal Input data to IR IR shift register Instruction Bypass Parallel output of IR Note Input data to TDR TDR shift register Old data New instruction...

  • Page 140: Initializing Tap Controller

    CHAPTER 6 JTAG BOUNDARY SCAN Initializing TAP Controller The TAP controller is initialized as follows: (1) The TAP controller is not initialized by the operation of system input such as system reset. (2) The TAP controller enters the Test-Logic-Reset controller state at the fifth rising edge of the TCK pin signal (while the TMS pin signal is held high).

  • Page 141: Bypass Instruction

    CHAPTER 6 JTAG BOUNDARY SCAN 6.7.1 BYPASS instruction This instruction is specified by instruction data “11”. This instruction is used to select only the bypass register (to access between the TDI and TDO pins serially) in the Shift-DR controller state. While this instruction is selected, the operation of the JTAG boundary scan circuit does not affect the operation of µ...
  • Page 142 Regional Information Some information contained in this document may vary from country to country. Before using any NEC Electronics product in your application, pIease contact the NEC Electronics office in your country to obtain a list of authorized representatives and distributors. They will verify: •...

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