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2.8.5 Asserting interrupts
2.8.5.1 Detecting hardware interrupts
Figure 2-88 shows how the hardware interrupts are readable through the Cause register.
The timer interrupt signal, IP7, is directly readable as bit 15 of the Cause register.
Bits 4 to 0 of the Interrupt register are bit-wise ORed with the current value of the Int4 to 0 signals and the result is
directly readable as bits 14 to 10 of the Cause register.
IP1 and IP0 of the Cause register, which are described in Section 2.5 Exception Processing, are software
interrupts. There is no hardware mechanism for setting or clearing the software interrupts.
Timer interrupt
MasterOut
CHAPTER 2 V
R
Figure 2-88. Hardware Interrupt Signals
4
3
2
1
0
Interrupt register (4:0)
4
3
2
1
0
(Internal register)
Int3
Int1
Int4
Int2
Int0
Preliminary User's Manual S15543EJ1V0UM
4120A
10
IP2
11
IP3
12
IP4
See Figure 2-53
13
IP5
IP6
14
15
IP7
Cause register
(15:10)
183
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