Table of Contents
Advertisement
(7) Status after reset
The contents of the Status register are undefined after Cold resets, except for the following bits in the diagnostic
status field.
•
TS and SR are cleared to 0.
•
ERL and BEV are set to 1.
•
SR is 0 after Cold reset, and is 1 after Soft reset or NMI interrupt.
Remark
Cold reset and Soft reset are CPU core reset (see Section 2.6 Initialization Interface).
2.5.3.6 Cause register (13)
The 32-bit read/write Cause register holds the cause of the most recent exception. A 5-bit exception code
indicates one of the causes (see Table 2-35). Other bits hold the detailed information of the specific exception. All
bits in the Cause register, with the exception of the IP1 and IP0 bits, are read-only; IP1 and IP0 are used for software
interrupts. Figure 2-53 shows the fields of this register; Table 2-35 describes the Cause register codes.
31 30 29 28
BD 0
1
1
: Indicates whether the most recent exception occurred in the branch delay slot (1 → In delay slot, 0
BD
→ Normal).
CE
: Indicates the coprocessor number in which a Coprocessor Unusable exception occurred.
This field will remain undefined for as long as no exception occurs.
: Indicates whether an interrupt is pending (1 → Interrupt pending, 0 → No interrupt pending).
IP
IP7
: A timer interrupt.
IP(6:2)
: Ordinary interrupts (Int(4:0)
IP(1:0)
: Software interrupts. Only these bits cause an interrupt exception, when they are set to 1 by
means of software.
Note Int (4:0) are internal signals of the CPU core. For details about connection to the on-chip
peripheral units.
ExcCode: Exception code field (refer to Table 2-35 for details).
0
: RFU. Write 0 in a write operation. When this field is read, 0 is read.
136
CHAPTER 2 V
Figure 2-53. Cause Register Format
27
CE
0
2
12
Note
Preliminary User's Manual S15543EJ1V0UM
4120A
R
16 15
8
7
6
IP(7:0)
0
ExcCode
8
1
Note
). However, Int4
never occurs in the V
2
1
0
0
5
2
4120A CPU.
R
Advertisement
Table of Contents
