Chapter 2 Pci Interface; How Should The Cache Line Size Of The Pci Configuration Register Be Set; Which Pci Commands Are Issued By The Μ Pd98409 When It Is The Master; How Should The Latency Timer Of The Pci Configuration Register Be Set - NEC mPD98409 Q&A

Q.2.1

How should the Cache line size of the PCI configuration register be set?

A.2.1
The Cache line size setting is not related to the burst size when the µ PD98409 performs transfer as the master.
The burst size is determined by the settings of the AD, TBE, and SZ fields in the GMR register.
The Cache line size setting, however, is related to PCI commands issued by the µ PD98409 (see Q.2.2).
Reference: µ PD98409 User's Manual 4.1.2 Configuration register
Q.2.2
Which PCI commands are issued by the µ PD98409 when it is the master?
A.2.2
Refer to 4.1.3 (2) Master transaction in the µ PD98409 User's Manual. Regarding read commands, however, the
command issued differs depending on the Cache line size setting.
When the Cache line size is set to 4, 8, or 16, the commands shown in 4.1.3 (2) (a) Read transaction in the
µ PD98409 User's Manual are issued.
When the Cache line size is set to other than 4, 8, or 16, the µ PD98409 always issues a memory read command.
Caution is therefore required when using the µ PD98409 in a system that performs processing via read command
type identification.
Reference: µ PD98409 User's Manual 4.1.3 (2) Master transaction
Q.2.3

How should the Latency timer of the PCI configuration register be set?

A.2.3
The Latency timer setting is valid when the lower 3 bits of the set value are masked.
In other words, the Latency timer setting should be 0, 8, 16, ..., 248.
Reference: µ PD98409 User's Manual 4.1.2 Configuration register
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CHAPTER 2 PCI INTERFACE

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