NEC 78K/0 Series Manuals

• 12

  Table of Contents

33

Chapter 1 Outline

• 33

  Features
• 34

  Applications
• 35

  Ordering Information
• 38

  Pin Configuration (Top View)
• 40

  K1 Family Lineup
  • 40

    78K0/Kx1 Product Lineup
  • 42

    V850Es/Kx1 Product Lineup
• 44

  Block Diagram
• 45

  Outline of Functions

47

Chapter 2 Pin Functions

• 47

  Pin Function List
• 51

  Description of Pin Functions
  • 51

    P00 to P06 (Port 0)
  • 52

    P10 to P17 (Port 1)
  • 52

    P20 to P27 (Port 2)
  • 53

    P30 to P33 (Port 3)
  • 53

    P40 to P47 (Port 4)
  • 53

    P50 to P57 (Port 5)
  • 54

    P60 to P67 (Port 6)
  • 54

    P70 to P77 (Port 7)
  • 54

    P120 (Port 12)
  • 54

    P130 (Port 13)
  • 55

    P140 to P145 (Port 14)
  • 55

    Av Ref
  • 55

    Av Ss
  • 56

    Reset
  • 56

    Regc
  • 56

    X1 and X2
  • 56

    XT1 and XT2
  • 56

    VDD and EV DD
  • 56

    VSS and EV SS
• 57

  Pin I/O Circuits and Recommended Connection of Unused Pins

61

Chapter 3 Cpu Architecture

• 61

  Memory Space
  • 67

    Internal Program Memory Space
  • 68

    Internal Data Memory Space
  • 68

    Special Function Register (SFR) Area
  • 69

    Data Memory Addressing
    • 74

      Processor Registers
      • 74

        Control Registers
      • 78

        General-Purpose Registers
      • 79

        Special Function Registers (Sfrs)
    • 84

      Instruction Address Addressing
      • 84

        Relative Addressing
      • 85

        Immediate Addressing
      • 86

        Register Addressing
    • 87

      Operand Address Addressing
      • 87

        Implied Addressing
      • 88

        Register Addressing
      • 89

        Direct Addressing
      • 90

        Short Direct Addressing
      • 91

        Special Function Register (SFR) Addressing
      • 92

        Register Indirect Addressing
      • 93

        Based Addressing
      • 94

        Based Indexed Addressing
      • 95

        Stack Addressing

96

Chapter 4 Port Functions

• 96

  Port Functions
• 98

  Port Configuration
  • 99

    Port 0
  • 103

    Port 1
  • 108

    Port 2
  • 109

    Port 3
  • 111

    Port 4
  • 112

    Port 5
  • 113

    Port 6
  • 116

    Port 7
  • 117

    Port 12
  • 118

    Port 13
  • 119

    Port 14
    • 120

      Block Diagram of P142
    • 121

      Block Diagram of P143
    • 122

      Block Diagram of P144 and P145
    • 123

      Format of Port Mode Register
    • 123

      Registers Controlling Port Function
    • 126

      Format of Port Register
    • 127

      Format of Pull-Up Resistor Option Register
    • 128

      Port Function Operations
      • 128

        Writing to I/O Port
      • 128

        Reading from I/O Port
      • 128

        Operations on I/O Port

129

Chapter 5 External Bus Interface

• 129

  External Bus Interface
• 130

  Memory Map When Using External Bus Interface
• 132

  Registers Controlling External Bus Interface
• 132

  Format of Memory Expansion Mode Register (MEM)
• 133

  Pins Specified for Address (with Μ PD780143)
• 134

  Format of Memory Expansion Wait Setting Register (MM)
• 135

  External Bus Interface Function Timing
• 136

  Instruction Fetch from External Memory
• 137

  External Memory Read Timing
• 138

  External Memory Write Timing
• 139

  External Memory Read Modify Write Timing
• 140

  Example of Connection with Memory
• 140

  Connection Example of Μ PD780144 and Memory

141

Chapter 6 Clock Generator

• 141

  Functions of Clock Generator
• 141

  Configuration of Clock Generator
• 142

  Block Diagram of Clock Generator
• 143

  Registers Controlling Clock Generator
• 144

  Format of Processor Clock Control Register (PCC)
• 145

  Format of Ring-OSC Mode Register (RCM)
• 146

  Format of Main Clock Mode Register (MCM)
• 147

  Format of Main OSC Control Register (MOC)
• 148

  Format of Oscillation Stabilization Time Counter Status Register (OSTC)
• 149

  Format of Oscillation Stabilization Time Select Register (OSTS)
• 150

  System Clock Oscillator
  • 150

    X1 Oscillator
  • 150

    Subsystem Clock Oscillator
  • 150

    Examples of External Circuit of X1 Oscillator
  • 150

    Examples of External Circuit of Subsystem Clock Oscillator
  • 151

    Examples of Incorrect Resonator Connection
  • 153

    When Subsystem Clock Is Not Used
  • 153

    Ring-OSC Oscillator
  • 153

    Prescaler
  • 153

    Subsystem Clock Feedback Resistor
• 154

  Clock Generator Operation
• 155

  Timing Diagram of CPU Default Start Using Ring-OSC
• 156

  Status Transition Diagram
• 161

  Time Required to Switch between Ring-OSC Clock and X1 Input Clock
• 162

  Time Required for CPU Clock Switchover
• 163

  Clock Switching Flowchart and Register Setting
  • 163

    Switching from Ring-OSC Clock to X1 Input Clock
  • 163

    Switching from Ring-OSC Clock to X1 Input Clock (Flowchart)
  • 164

    Switching from X1 Input Clock to Ring-OSC Clock
  • 164

    Switching from X1 Input Clock to Ring-OSC Clock (Flowchart)
  • 165

    Switching from X1 Input Clock to Subsystem Clock
  • 165

    Switching from X1 Input Clock to Subsystem Clock (Flowchart)
  • 166

    Switching from Subsystem Clock to X1 Input Clock
  • 166

    Switching from Subsystem Clock to X1 Input Clock (Flowchart)
  • 167

    Register Settings

168

Chapter 7 16-Bit Timer/Event Counters 00 and 01

• 168

  Functions of 16-Bit Timer/Event Counters 00 and 01
• 169

  Configuration of 16-Bit Timer/Event Counters 00 and 01
• 169

  Block Diagram of 16-Bit Timer/Event Counter 00
• 170

  PD780146, 780148, and 78F0148 Only)
• 171

  Format of 16-Bit Timer Counter 0N (Tm0N)
• 171

  Format of 16-Bit Timer Capture/Compare Register 00N (Cr00N)
• 173

  Format of 16-Bit Timer Capture/Compare Register 01N (Cr01N)
• 174

  Registers Controlling 16-Bit Timer/Event Counters 00 and 01
• 175

  Format of 16-Bit Timer Mode Control Register 00 (TMC00)
• 176

  Format of 16-Bit Timer Mode Control Register 01 (TMC01)
• 177

  Format of Capture/Compare Control Register 00 (CRC00)
• 178

  Format of Capture/Compare Control Register 01 (CRC01)
• 179

  Format of 16-Bit Timer Output Control Register 00 (TOC00)
• 180

  Format of 16-Bit Timer Output Control Register 01 (TOC01)
• 182

  Format of Prescaler Mode Register 00 (PRM00)
• 183

  Format of Prescaler Mode Register 01 (PRM01)
• 184

  Format of Port Mode Register 0 (PM0)
• 185

  Operation of 16-Bit Timer/Event Counters 00 and 01
  • 185

    Interval Timer Operation
  • 186

    Control Register Settings for Interval Timer Operation
  • 187

    Interval Timer Configuration Diagram
  • 187

    Timing of Interval Timer Operation
  • 188

    PPG Output Operations
  • 189

    Control Register Settings for PPG Output Operation
  • 190

    Configuration Diagram of PPG Output
  • 190

    PPG Output Operation Timing
  • 191

    Pulse Width Measurement Operations
  • 191

    Cr01N Capture Operation with Rising Edge Specified
  • 192

    And One Capture Register (When Ti00N and Cr01N Are Used)
  • 193

    Configuration Diagram for Pulse Width Measurement with Free-Running Counter
  • 193

    And One Capture Register (with both Edges Specified)
  • 194

    Control Register Settings for Measurement of Two Pulse Widths with Free-Running Counter
  • 195

    (With both Edges Specified)
  • 196

    Two Capture Registers (with Rising Edge Specified)
  • 197

    And Two Capture Registers (with Rising Edge Specified)
  • 198

    (With Rising Edge Specified)
  • 198

    Timing of Pulse Width Measurement Operation by Means of Restart (with Rising Edge Specified)
  • 199

    External Event Counter Operation
  • 200

    Control Register Settings in External Event Counter Mode (with Rising Edge Specified)
  • 201

    Configuration Diagram of External Event Counter
  • 201

    External Event Counter Operation Timing (with Rising Edge Specified)
  • 202

    Square-Wave Output Operation
  • 202

    Control Register Settings in Square-Wave Output Mode
  • 203

    Square-Wave Output Operation Timing
  • 204

    One-Shot Pulse Output Operation
  • 205

    Control Register Settings for One-Shot Pulse Output with Software Trigger
  • 206

    Timing of One-Shot Pulse Output Operation with Software Trigger
  • 207

    (With Rising Edge Specified)
  • 208

    Timing of One-Shot Pulse Output Operation with External Trigger (with Rising Edge Specified)
• 209

  Cautions for 16-Bit Timer/Event Counters 00 and 01
• 209

  Start Timing of 16-Bit Timer Counter 0N (Tm0N)

212

Chapter 8 8-Bit Timer/Event Counters 50 and 51

• 212

  Functions of 8-Bit Timer/Event Counters 50 and 51
• 214

  Configuration of 8-Bit Timer/Event Counters 50 and 51
• 216

  Registers Controlling 8-Bit Timer/Event Counters 50 and 51
• 221

  Operations of 8-Bit Timer/Event Counters 50 and 51
  • 221

    Operation as Interval Timer
  • 223

    Operation as External Event Counter
  • 224

    Square-Wave Output Operation
  • 225

    PWM Output Operation
• 229

  Cautions for 8-Bit Timer/Event Counters 50 and 51

230

Chapter 9 8-Bit Timers H0 and H1

• 230

  Functions of 8-Bit Timers H0 and H1
• 230

  Configuration of 8-Bit Timers H0 and H1
• 234

  Registers Controlling 8-Bit Timers H0 and H1
• 239

  Operation of 8-Bit Timers H0 and H1
  • 239

    Operation as Interval Timer/Square-Wave Output
  • 242

    Operation as PWM Output Mode
  • 248

    Carrier Generator Mode Operation (8-Bit Timer H1 Only)

255

Chapter 10 Watch Timer

• 255

  Functions of Watch Timer
• 257

  Configuration of Watch Timer
• 257

  Register Controlling Watch Timer
• 259

  Watch Timer Operations
  • 259

    Watch Timer Operation
  • 260

    Interval Timer Operation
  • 261

    Cautions for Watch Timer

262

Chapter 11 Watchdog Timer

• 262

  Functions of Watchdog Timer
• 264

  Configuration of Watchdog Timer
• 264

  Block Diagram of Watchdog Timer
• 265

  Registers Controlling Watchdog Timer
• 265

  Format of Watchdog Timer Mode Register (WDTM)
• 266

  Format of Watchdog Timer Enable Register (WDTE)
• 267

  Operation of Watchdog Timer
  • 267

    Watchdog Timer Operation When "Ring-OSC Cannot be Stopped" Is Selected by Mask Option
  • 268

    Watchdog Timer Operation When "Ring-OSC Can be Stopped by Software" Is Selected by Mask Option
  • 269

    Watchdog Timer Operation in STOP Mode (When "Ring-OSC Can be Stopped by Software" Is Selected by Mask Option)
  • 269

    Operation in STOP Mode (CPU Clock and WDT Operation Clock: X1 Input Clock)
  • 269

    Operation in STOP Mode (CPU Clock: X1 Input Clock, WDT Operation Clock: Ring-OSC Clock)
  • 270

    Operation in STOP Mode (CPU Clock: Ring-OSC Clock, WDT Operation Clock: X1 Input Clock)
  • 271

    Watchdog Timer Operation in HALT Mode (When "Ring-OSC Can be Stopped by Software" Is Selected by Mask Option)
  • 271

    Operation in STOP Mode (CPU Clock and WDT Operation Clock: Ring-OSC Clock)
  • 271

    Operation in HALT Mode

272

Chapter 12 Clock Output/Buzzer Output Controller

• 272

  Functions of Clock Output/Buzzer Output Controller
• 272

  Block Diagram of Clock Output/Buzzer Output Controller
• 273

  Configuration of Clock Output/Buzzer Output Controller
• 273

  Register Controlling Clock Output/Buzzer Output Controller
• 274

  Format of Clock Output Selection Register (CKS)
• 275

  Format of Port Mode Register 14 (PM14)
• 276

  Clock Output/Buzzer Output Controller Operations
  • 276

    Clock Output Operation
  • 276

    Operation as Buzzer Output
  • 276

    Remote Control Output Application Example

277

Chapter 13 A/D Converter

• 277

  Functions of A/D Converter
• 277

  Block Diagram of A/D Converter
• 278

  Configuration of A/D Converter
• 280

  Registers Used in A/D Converter
• 281

  Format of A/D Converter Mode Register (ADM)
• 282

  Timing Chart When Boost Reference Voltage Generator Is Used
• 283

  Format of Analog Input Channel Specification Register (ADS)
• 284

  Format of A/D Conversion Result Register (ADCR)
• 285

  Format of Power-Fail Comparison Mode Register (PFM)
• 285

  Format of Power-Fail Comparison Threshold Register (PFT)
• 286

  A/D Converter Operations
  • 286

    Basic Operations of A/D Converter
  • 287

    Basic Operation of A/D Converter
  • 288

    Input Voltage and Conversion Results
  • 288

    Relationship between Analog Input Voltage and A/D Conversion Result
  • 289

    A/D Converter Operation Mode
  • 289

    A/D Conversion Operation
  • 290

    Power-Fail Detection (When PFEN = 1 and PFCM = 0)
  • 292

    How to Read A/D Converter Characteristics Table
  • 292

    Overall Error
  • 292

    Quantization Error
  • 293

    Zero-Scale Error
  • 293

    Full-Scale Error
  • 293

    Integral Linearity Error
  • 293

    Differential Linearity Error
  • 294

    Cautions for A/D Converter
  • 294

    Circuit Configuration of Series Resistor String
  • 295

    Analog Input Pin Connection
  • 296

    Timing of A/D Conversion End Interrupt Request Generation
  • 297

    Timing of A/D Converter Sampling and A/D Conversion Start Delay
  • 298

    Internal Equivalent Circuit of Anin Pin

299

Chapter 14 Serial Interface Uart0

• 299

  Functions of Serial Interface UART0
• 300

  Configuration of Serial Interface UART0
• 301

  Block Diagram of Serial Interface UART0
• 303

  Registers Controlling Serial Interface UART0
• 303

  Format of Asynchronous Serial Interface Operation Mode Register 0 (ASIM0)
• 305

  Format of Asynchronous Serial Interface Reception Error Status Register 0 (ASIS0)
• 306

  Format of Baud Rate Generator Control Register 0 (BRGC0)
• 307

  Format of Port Mode Register 1 (PM1)
• 308

  Operation of Serial Interface UART0
  • 308

    Operation Stop Mode
  • 309

    Asynchronous Serial Interface (UART) Mode
  • 310

    Format of Normal UART Transmit/Receive Data
  • 310

    Example of Normal UART Transmit/Receive Data Waveform
  • 312

    Transmission Completion Interrupt Request Timing
  • 313

    Reception Completion Interrupt Request Timing
  • 314

    Noise Filter Circuit
  • 315

    Dedicated Baud Rate Generator
  • 315

    Configuration of Baud Rate Generator
  • 318

    Permissible Baud Rate Range During Reception

320

Chapter 15 Serial Interface Uart6

• 320

  Functions of Serial Interface UART6
• 321

  LIN Transmission Operation
• 322

  LIN Reception Operation
• 323

  Port Configuration for LIN Reception Operation
• 324

  Configuration of Serial Interface UART6
• 325

  Block Diagram of Serial Interface UART6
• 327

  Registers Controlling Serial Interface UART6
• 327

  Format of Asynchronous Serial Interface Operation Mode Register 6 (ASIM6)
• 329

  Format of Asynchronous Serial Interface Reception Error Status Register 6 (ASIS6)
• 330

  Format of Asynchronous Serial Interface Transmission Status Register 6 (ASIF6)
• 331

  Format of Clock Selection Register 6 (CKSR6)
• 332

  Format of Baud Rate Generator Control Register 6 (BRGC6)
• 333

  Format of Asynchronous Serial Interface Control Register 6 (ASICL6)
• 334

  Format of Input Switch Control Register (ISC)
• 334

  Format of Port Mode Register 1 (PM1)
• 335

  Operation of Serial Interface UART6
  • 335

    Operation Stop Mode
  • 336

    Asynchronous Serial Interface (UART) Mode
  • 338

    Format of Normal UART Transmit/Receive Data
  • 339

    Example of Normal UART Transmit/Receive Data Waveform
  • 341

    Normal Transmission Completion Interrupt Request Timing
  • 343

    Example of Continuous Transmission Processing Flow
  • 344

    Timing of Starting Continuous Transmission
  • 345

    Timing of Ending Continuous Transmission
  • 346

    Reception Completion Interrupt Request Timing
  • 347

    Reception Error Interrupt
  • 348

    Noise Filter Circuit
  • 349

    Example of Setting Procedure of SBF Transmission (Flowchart)
  • 349

    SBF Transmission
  • 350

    SBF Reception
  • 351

    Dedicated Baud Rate Generator
  • 352

    Configuration of Baud Rate Generator
  • 355

    Permissible Baud Rate Range During Reception
  • 357

    Data Frame Length During Continuous Transmission

358

Chapter 16 Serial Interfaces Csi10 and Csi11

• 358

  Functions of Serial Interfaces CSI10 and CSI11
• 359

  Configuration of Serial Interfaces CSI10 and CSI11
• 359

  Block Diagram of Serial Interface CSI10
• 360

  PD780146, 780148, and 78F0148 Only)
• 361

  Registers Controlling Serial Interfaces CSI10 and CSI11
• 361

  Format of Serial Operation Mode Register 10 (CSIM10)
• 362

  Format of Serial Operation Mode Register 11 (CSIM11)
• 363

  Format of Serial Clock Selection Register 10 (CSIC10)
• 365

  Format of Serial Clock Selection Register 11 (CSIC11)
• 366

  Format of Port Mode Register 0 (PM0)
• 366

  Format of Port Mode Register 1 (PM1)
• 367

  Operation of Serial Interfaces CSI10 and CSI11
  • 367

    Operation Stop Mode
  • 368

    3-Wire Serial I/O Mode
  • 372

    Timing in 3-Wire Serial I/O Mode
  • 374

    Timing of Clock/Data Phase
  • 375

    Output Operation of First Bit
  • 376

    Output Value of So1N Pin (Last Bit)

378

Chapter 17 Serial Interface Csia0

• 378

  Functions of Serial Interface CSIA0
• 379

  Configuration of Serial Interface CSIA0
• 380

  Block Diagram of Serial Interface CSIA0
• 381

  Registers Controlling Serial Interface CSIA0
• 381

  Format of Automatic Data Transfer Address Count Register 0 (ADTC0)
• 382

  Format of Serial Operation Mode Specification Register 0 (CSIMA0)
• 383

  Format of Serial Status Register 0 (CSIS0)
• 385

  Format of Serial Trigger Register 0 (CSIT0)
• 386

  Format of Divisor Selection Register 0 (BRGCA0)
• 386

  Format of Automatic Data Transfer Address Point Specification Register 0 (ADTP0)
• 388

  Format of Automatic Data Transfer Interval Specification Register 0 (ADTI0)
• 389

  Format of Port Mode Register 14 (PM14)
• 390

  Operation of Serial Interface CSIA0
  • 390

    Operation Stop Mode
  • 391

    3-Wire Serial I/O Mode
  • 393

    3-Wire Serial I/O Mode Timing
  • 394

    Format of Transmit/Receive Data
  • 395

    Transfer Bit Order Switching Circuit
  • 396

    3-Wire Serial I/O Mode with Automatic Transmit/Receive Function
  • 399

    Automatic Transmission/Reception Mode Operation Timings
  • 400

    Automatic Transmission/Reception Mode Flowchart
  • 401

    (In Automatic Transmission/Reception Mode) (1/2
  • 403

    Automatic Transmission Mode Operation Timing
  • 404

    Automatic Transmission Mode Flowchart
  • 405

    Internal Buffer RAM Operation in 6-Byte Transmission (in Automatic Transmission Mode)
  • 407

    Repeat Transmission Mode Operation Timing
  • 408

    Repeat Transmission Mode Flowchart
  • 409

    Internal Buffer RAM Operation in 6-Byte Transmission (in Repeat Transmission Mode)
  • 411

    Format of CSIA0 Transmit/Receive Data
  • 412

    Automatic Transmission/Reception Suspension and Restart
  • 413

    System Configuration When Busy Control Option Is Used
  • 414

    Operation Timing When Busy Control Option Is Used (When BUSYLV0 = 1)
  • 414

    Busy Signal and Wait Release (When BUSYLV0 = 1)
  • 415

    Operation Timing When Busy & Strobe Control Options Are Used (When BUSYLV0 = 1)
  • 416

    Operation Timing of Bit Shift Detection Function by Busy Signal (When BUSYLV0 = 0)
  • 417

    Automatic Transmit/Receive Interval Time

418

Chapter 18 Multiplier/Divider

• 418

  Functions of Multiplier/Divider
• 418

  Configuration of Multiplier/Divider
• 423

  Register Controlling Multiplier/Divider
• 424

  Operations of Multiplier/Divider
  • 424

    Multiplication Operation
  • 426

    Division Operation

428

Chapter 19 Interrupt Functions

• 428

  Interrupt Function Types
• 428

  Interrupt Sources and Configuration
• 432

  Registers Controlling Interrupt Functions
• 439

  Interrupt Servicing Operations
  • 439

    Maskable Interrupt Request Acknowledgement
  • 441

    Software Interrupt Request Acknowledgment
  • 442

    Multiple Interrupt Servicing
  • 445

    Interrupt Request Hold

446

Chapter 20 Key Interrupt Function

• 446

  Functions of Key Interrupt
• 446

  Configuration of Key Interrupt
• 447

  Register Controlling Key Interrupt

448

Chapter 21 Standby Function

• 448

  Standby Function and Configuration
  • 448

    Standby Function
  • 450

    Registers Controlling Standby Function
  • 452

    Standby Function Operation
    • 452

      HALT Mode
    • 457

      STOP Mode

461

Chapter 22 Reset Function

• 468

  Register for Confirming Reset Source

469

Chapter 23 Clock Monitor

• 469

  Functions of Clock Monitor
• 469

  Configuration of Clock Monitor
• 470

  Registers Controlling Clock Monitor
• 471

  Operation of Clock Monitor

• 10

  Table of Contents

17

Chapter 1 Outline

• 17

  Features
• 18

  Applications
• 19

  Ordering Information
• 21

  Pin Configuration (Top View)
• 23

  K1 Family Lineup
  • 23

    78K0/Kx1 Product Lineup
  • 25

    V850Es/Kx1 Product Lineup
• 27

  Block Diagram
• 28

  Outline of Functions

30

Chapter 2 Pin Functions

• 30

  Pin Function List
• 33

  Description of Pin Functions
  • 33

    P00 and P01 (Port 0)
  • 34

    P10 to P17 (Port 1)
  • 34

    P20 to P27 (Port 2)
  • 35

    P30 to P33 (Port 3)
  • 35

    P60 to P63 (Port 6)
  • 35

    P70 to P73 (Port 7)
  • 36

    P120 (Port 12)
  • 36

    P130 (Port 13)
  • 36

    Av Ref
  • 36

    Av Ss
  • 36

    Reset
  • 36

    X1 and X2
  • 37

    IC (Mask ROM Versions Only)
• 38

  Pin I/O Circuits and Recommended Connection of Unused Pins

41

Chapter 3 Cpu Architecture

• 41

  Memory Space
  • 47

    Internal Program Memory Space
  • 48

    Internal Data Memory Space
  • 48

    Special Function Register (SFR) Area
  • 49

    Data Memory Addressing
• 54

  Processor Registers
  • 54

    Control Registers
  • 58

    General-Purpose Registers
  • 59

    Special Function Registers (Sfrs)
• 63

  Instruction Address Addressing
  • 63

    Relative Addressing
    • 64

      Immediate Addressing
    • 65

      Register Addressing
    • 65

      Table Indirect Addressing
    • 66

      Operand Address Addressing
      • 66

        Implied Addressing
      • 67

        Register Addressing
      • 68

        Direct Addressing
      • 69

        Short Direct Addressing
      • 70

        Special Function Register (SFR) Addressing
      • 71

        Register Indirect Addressing
      • 72

        Based Addressing
      • 73

        Based Indexed Addressing
      • 74

        Stack Addressing

75

Chapter 4 Port Functions

• 75

  Port Functions
• 77

  Port Configuration
  • 78

    Port 0
  • 80

    Port 1
  • 85

    Port 2
  • 86

    Port 3
  • 88

    Port 6
  • 89

    Port 7
  • 90

    Port 12
  • 91

    Port 13
  • 92

    Registers Controlling Port Function
  • 96

    Port Function Operations
    • 96

      Writing to I/O Port
    • 96

      Reading From I/O Port
    • 96

      Operations On I/O Port

97

Chapter 5 Clock Generator

• 97

  Functions of Clock Generator
• 97

  Configuration of Clock Generator
• 99

  Registers Controlling Clock Generator
• 106

  System Clock Oscillator
  • 106

    X1 Oscillator
  • 106

    Subsystem Clock Oscillator
  • 109

    When Subsystem Clock Is Not Used
  • 109

    Ring-Osc Oscillator
  • 109

    Prescaler
  • 110

    Clock Generator Operation
  • 117

    Time Required to Switch Between Ring-Osc Clock and X1 Input Clock
  • 118

    Time Required for CPU Clock Switchover
  • 119

    Clock Switching Flowchart and Register Setting
    • 119

      Switching From Ring-Osc Clock to X1 Input Clock
    • 120

      Switching From X1 Input Clock to Ring-Osc Clock
    • 121

      Switching From X1 Input Clock to Subsystem Clock
    • 122

      Switching From Subsystem Clock to X1 Input Clock
    • 123

      Register Settings

124

Chapter 6 16-Bit Timer/Event Counter 00

• 124

  Functions of 16-Bit Timer/Event Counter 00
• 125

  Configuration of 16-Bit Timer/Event Counter 00
• 129

  Registers Controlling 16-Bit Timer/Event Counter 00
• 135

  Operation of 16-Bit Timer/Event Counter 00
  • 135

    Interval Timer Operation
  • 137

    PPG Output Operations
  • 140

    Pulse Width Measurement Operations
  • 148

    External Event Counter Operation
  • 150

    Square-Wave Output Operation
  • 152

    One-Shot Pulse Output Operation
• 157

  Cautions for 16-Bit Timer/Event Counter 00

160

Chapter 7 8-Bit Timer/Event Counters 50 and 51

• 160

  Functions of 8-Bit Timer/Event Counters 50 and 51
• 162

  Configuration of 8-Bit Timer/Event Counters 50 and 51
• 164

  Registers Controlling 8-Bit Timer/Event Counters 50 and 51
• 169

  Operations of 8-Bit Timer/Event Counters 50 and 51
  • 169

    Operation As Interval Timer
  • 171

    Operation As External Event Counter
  • 172

    Square-Wave Output Operation
  • 173

    PWM Output Operation
• 177

  Cautions for 8-Bit Timer/Event Counters 50 and 51

178

Chapter 8 8-Bit Timers H0 and H1

• 178

  Functions of 8-Bit Timers H0 and H1
• 178

  Configuration of 8-Bit Timers H0 and H1
• 182

  Registers Controlling 8-Bit Timers H0 and H1
• 186

  Operation of 8-Bit Timers H0 and H1
  • 186

    Operation As Interval Timer/Square-Wave Output
  • 189

    Operation As PWM Output Mode
  • 195

    Carrier Generator Mode Operation (8-Bit Timer H1 Only)

202

Chapter 9 Watch Timer

• 202

  Functions of Watch Timer
• 204

  Configuration of Watch Timer
• 204

  Register Controlling Watch Timer
• 206

  Watch Timer Operations
  • 206

    Watch Timer Operation
  • 207

    Interval Timer Operation
• 208

  Cautions for Watch Timer

209

Chapter 10 Watchdog Timer

• 209

  Functions of Watchdog Timer
  • 211

    Configuration of Watchdog Timer
  • 212

    Registers Controlling Watchdog Timer
  • 214

    Operation of Watchdog Timer
    • 214

      Watchdog Timer Operation When "Ring-Osc Cannot Be Stopped" Is Selected By Mask Option
    • 215

      Watchdog Timer Operation When "Ring-Osc Can Be Stopped By Software" Is Selected By Mask Option
    • 216

      Watchdog Timer Operation in STOP Mode (When "Ring-Osc Can Be Stopped By Software" Is Selected By Mask Option)
    • 218

      Watchdog Timer Operation in HALT Mode (When "Ring-Osc Can Be Stopped By Software" Is Selected By Mask Option)

219

Chapter 11 A/D Converter

• 219

  Functions of A/D Converter
• 220

  Configuration of A/D Converter
• 222

  Registers Used in A/D Converter
• 227

  A/D Converter Operations
  • 227

    Basic Operations of A/D Converter
  • 229

    Input Voltage and Conversion Results
  • 230

    A/D Converter Operation Mode
  • 233

    How to Read A/D Converter Characteristics Table
  • 235

    Cautions for A/D Converter

240

Chapter 12 Serial Interface Uart0

• 240

  Functions of Serial Interface UART0
• 241

  Configuration of Serial Interface UART0
• 244

  Registers Controlling Serial Interface UART0
• 249

  Operation of Serial Interface UART0
  • 249

    Operation Stop Mode
  • 250

    Asynchronous Serial Interface (UART) Mode
  • 256

    Dedicated Baud Rate Generator

261

Chapter 13 Serial Interface Uart6

• 261

  Functions of Serial Interface UART6
• 265

  Configuration of Serial Interface UART6
• 268

  Registers Controlling Serial Interface UART6
• 276

  Operation of Serial Interface UART6
  • 276

    Operation Stop Mode
  • 277

    Asynchronous Serial Interface (UART) Mode
  • 292

    Dedicated Baud Rate Generator

299

Chapter 14 Serial Interface Csi10

• 299

  Functions of Serial Interface CSI10
• 299

  Configuration of Serial Interface CSI10
• 301

  Registers Controlling Serial Interface CSI10
• 304

  Operation of Serial Interface CSI10
  • 304

    Operation Stop Mode
  • 305

    3-Wire Serial I/O Mode

313

Chapter 15 Interrupt Functions

• 313

  Interrupt Function Types
• 313

  Interrupt Sources and Configuration
• 316

  Registers Controlling Interrupt Functions
• 323

  Interrupt Servicing Operations
  • 323

    Maskable Interrupt Request Acknowledgment
  • 325

    Software Interrupt Request Acknowledgment
  • 326

    Multiple Interrupt Servicing
  • 329

    Interrupt Request Hold

330

Chapter 16 Key Interrupt Function

• 330

  Functions of Key Interrupt
• 330

  Configuration of Key Interrupt
• 331

  Register Controlling Key Interrupt

332

Chapter 17 Standby Function

• 332

  Standby Function and Configuration
  • 332

    Standby Function
  • 334

    Registers Controlling Standby Function
• 336

  Standby Function Operation
  • 336

    HALT Mode
  • 341

    STOP Mode

345

Chapter 18 Reset Function

• 351

  Register for Confirming Reset Source

352

Chapter 19 Clock Monitor

• 352

  Functions of Clock Monitor
• 352

  Configuration of Clock Monitor
• 353

  Register Controlling Clock Monitor
• 354

  Operation of Clock Monitor

359

Chapter 20 Power-On-Clear Circuit

• 359

  Functions of Power-On-Clear Circuit
• 360

  Configuration of Power-On-Clear Circuit
• 360

  Operation of Power-On-Clear Circuit
• 361

  Cautions for Power-On-Clear Circuit

363

Chapter 21 Low-Voltage Detector

• 363

  Functions of Low-Voltage Detector
• 363

  Configuration of Low-Voltage Detector
• 364

  Registers Controlling Low-Voltage Detector
• 367

  Operation of Low-Voltage Detector
• 371

  Cautions for Low-Voltage Detector

375

Chapter 22 Mask Options