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(e)
Stop condition
When the SCL pin is at high level (when serial transfer has been completed and a serial clock has not been
output), changing the SDA pin from low level to high level generates a stop condition.
A stop condition is a signal that the master device outputs to the slave device when serial transfer has been
completed.
4.2.2 Status transition diagram
Figure 4-7 shows the status transition diagram.
RESET
Wait for ST/SP
SP detected
2
CHAPTER 4 I
Figure 4-6. Stop Condition
H
SCL
SDA
Figure 4-7. Shift Register Operation
SP detected
ST
detected
Status 1
Status 2
Wait for ID (W)
SP detected
NACK reception
Status 9
Wait for SP
User's Manual U18438EJ2V0UD
C COMMUNICATIONS
ID
reception
Status 3
Wait for AD
WD reception
Status 5
Wait for WD/SP
WD reception
ACK reception
Status 8
Wait for ACK/NACK
RD transmission
AD
reception
Status 4
Wait for WD/RST
RST
detected
Status 6
Wait for ID (R)
ID
reception
Status 7
Wait for RD
53
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