Ispr - In-Service Priority Register; Maskable Interrupt Status Flag (Id) - NEC V850E/Dx3 Preliminary User's Manual

Chapter 5
ISPR
Bit position
7 to 0
PSW
Bit position
5
216
Downloaded from Elcodis.com electronic components distributor

5.3.6 ISPR - In-service priority register

This register holds the priority level of the maskable interrupt currently
acknowledged. When an interrupt request is acknowledged, the bit of this
register corresponding to the priority level of that interrupt request is set to 1
and remains set while the interrupt is serviced.
When the RETI instruction is executed, the bit corresponding to the interrupt
request having the highest priority is automatically reset to 0 by hardware.
However, it is not reset to 0 when execution is returned from non-maskable
interrupt servicing or exception processing.
This register is read-only in 8-bit or 1-bit units.
7 6 5
ISPR7 ISPR6 ISPR5
Bit name Function
ISPR7 to Indicates priority of interrupt currently acknowledged
ISPR0 0: Interrupt request with priority n not acknowledged
1: Interrupt request with priority n acknowledged
Note n = 0 to 7 (priority level)

5.3.7 Maskable interrupt status flag (ID)

The ID flag is bit 5 of the PSW and this controls the maskable interrupt's
operating state, and stores control information regarding enabling or disabling
of interrupt requests.
31
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NP
Bit name Function
ID Indicates whether maskable interrupt processing is enabled or disabled.
0: Maskable interrupt request acknowledgement enabled
1: Maskable interrupt request acknowledgement disabled (pending)
This bit is set to 1 by the DI instruction and reset to 0 by the EI instruction. Its value
is also modified by the RETI instruction or LDSR instruction when referencing to
PSW.
Non-maskable interrupt requests and exceptions are acknowledged regardless of
this flag. when a maskable interrupt is acknowledged, the ID flag is automatically
set to 1 by hardware.
The interrupt request generated during the acknowledgement disabled period
(ID = 1) is acknowledged when the PIFn bit of PICn register is set to 1, and the ID
flag is reset to 0.
Preliminary User's Manual U17566EE1V2UM00
4 3 2
ISPR4 ISPR3 ISPR2 ISPR1
8 7 6
EP
Interrupt Controller (INTC)
1 0 Address
ISPR0 FFFFF19AH
5 4 3 2 1 0
ID SAT CY OV S Z
Initial
value
00H
Initial value
00000020H