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5.3 Maskable Interrupts
Maskable interrupt requests can be masked by interrupt control registers.
If two or more maskable interrupt requests are generated at the same time,
they are acknowledged according to the default priority. In addition to the
default priority, eight levels of priorities can be specified by using the interrupt
control registers (programmable priority control).
When an interrupt request has been acknowledged, the acknowledgement of
other maskable interrupt requests is disabled and the interrupt disabled (DI)
status is set.
When the EI instruction is executed in an interrupt processing routine, the
interrupt enabled (EI) status is set, which enables servicing of interrupts having
a higher priority than the interrupt request in progress (specified by the
interrupt control register). Note that only interrupts with a higher priority will
have this capability; interrupts with the same priority level cannot be nested.
However, if multiple interrupts are executed, the following processing is
necessary.
(1)
Save EIPC and EIPSW in memory or a general-purpose register before
executing the EI instruction.
(2)
Execute the DI instruction before executing the RETI instruction, then
reset EIPC and EIPSW with the values saved in (1).
5.3.1 Operation
If a maskable interrupt occurs by INT input, the CPU performs the following
processing, and transfers control to a handler routine:
(1)
Saves the restored PC to EIPC.
(2)
Saves the current PSW to EIPSW.
(3)
Writes an exception code to the lower halfword of ECR (EICC).
(4)
Sets the ID bit of the PSW and clears the EP bit.
(5)
Sets the handler address corresponding to each interrupt to the PC, and
transfers control.
The processing configuration of a maskable interrupt is shown in Figure 5-5.
Preliminary User's Manual U17566EE1V2UM00
Chapter 5
203
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