NEC V850E/Dx3 Preliminary User's Manual page 466

Chapter 13
GCCn1 Slave register
GCCn1 Master register
466
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(f) When GCCnm (m = 1 to 4) is rewritten during operation (match and
clear)
When the value of GCCn1 is changed from 0555H to 0AAAH, the operation
described below is performed.
TMGn0 is selected as the counter, and 0FFFH is set in GCCn0.
ENFG0
Ma tch
TM G n0
0555H
INTTGnCC1
Figure 13-14 Timing when GCCnm is rewritten during operation (match and clear)
Caution To perform successive write access during operation, for rewriting the GCCny
register, you have to wait for minimum 7 peripheral clocks periods (f
(3) PMW output (match and clear)
Basic settings (m = 1 to 4):
Bit
CCSGn0
CCSGn5
SWFGnm
CCSGnm
TBGnm
Note The PWM mode is activated by setting the SWFGnm and the CCSGnm bit to
"1".
Preliminary User's Manual U17566EE1V2UM00
16-bit Multi-Purpose Timer G (TMG)
Reload in 5 clock periods
0555H
0AAAH
Value
1
1
Note
1
Note
1
X
Ma tch
0AAAH
).
SPCLK0
Remark
match and clear mode
enable TOGnm
Compare mode for
GCCnm
assign counter
for GCCnm
0: TMGn0
1: TMGn1