Wait Signal (Wait) - NEC V850E/Dx3 Preliminary User's Manual

2
I C Bus (IIC)
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18.6.6 Wait signal (WAIT)

The wait signal (WAIT) is used to notify the communication partner that a
device (master or slave) is preparing to transmit or receive data (i.e., is in a
wait state).
Setting the SCLn pin to low level notifies the communication partner of the wait
status. When the wait status has been cancelled for both the master and slave
devices, the next data transfer can begin.
(1) When master device has a nine-clock wait and slave device has an eight-
clock wait (master: transmission, slave: reception, and IICCn.ACKEn
bit = 1)
Master (Tx)
IICn
6
SCLn
Slave (Rx)
IICn
SCLn
H
ACKEn
Transfer lines
6
SCLn
SDAn
D2
Figure 18-11 Wait signal (1/2)
Preliminary User's Manual U17566EE1V2UM00
Master returns to high
Wait after output
impedance but slave
of ninth clock.
is in wait state (low level).
7 8 9
Wait after output
of eighth clock.
FFH is written to IICn register or
IICCn.WRELn bit is set to 1.
Wait signal
Wait signal
from master
from slave
7 8 9
D1 D0 ACK
Chapter 18
IICn data write (cancel wait)
1 2 3
1 2 3
D7 D6 D5
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